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參數(shù)資料
| 型號： | ICSSSTUAH32868AHLF |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| 中文描述： | 28位可配置注冊緩沖內(nèi)存 |
| 文件頁數(shù)： | 9/22頁 |
| 文件大?。?/td> | 468K |
| 代理商： | ICSSSTUAH32868AHLF |
ICSSSTUAH32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
9
ICSSSTUAH32868A
7115/9
Parity and Standby Function Table
Inputs
1
CLK
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
Outputs
QERR
3
RESET
DCS0
DCS1
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
Σ
of Inputs = H (D1 - D28)
PAR_IN
2
H
L
X
Even
L
H
H
L
X
Odd
L
L
H
L
X
Even
H
L
H
L
X
Odd
H
H
H
X
L
Even
L
H
H
X
L
Odd
L
L
H
X
L
Even
H
L
H
X
L
Odd
H
H
H
H
H
X
X
QERR
04
QERR
0
H
H
X
X
X
X
L
X or
Floating
X or
Floating
X or
Floating
X or
Floating
X or Floating
X or Floating
1
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑
= LOW to HIGH
↓
= HIGH to LOW
PAR_IN arrives one clock cycle after the data to which it applies.
This transition assumes QERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If
QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW.
4
If DCS0, DCS1, and CSGEN are driven HIGH, the device is placed in low-power mode (LPM). If a parity
error occurs on the clock cycle before the device enters the LPM and the QERR output is driven LOW, it stays
latched LOW for the LPM plus two clock cycles or until RESET is driven LOW.
2
3
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