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參數(shù)資料
| 型號(hào)： | ICSSSTUAH32868AHLF |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| 中文描述： | 28位可配置注冊(cè)緩沖內(nèi)存 |
| 文件頁(yè)數(shù)： | 19/22頁(yè) |
| 文件大?。?/td> | 468K |
| 代理商： | ICSSSTUAH32868AHLF |
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ICSSSTUAH32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
19
ICSSSTUAH32868A
7115/9
Test Circuits and Waveforms (V
DD
= 1.8V ± 0.1V)
Load Circuit: High-to-Low Slew-Rate Adjustment
Voltage Waveforms: High-to-Low Slew-Rate Adjustment
Load Circuit: Low-to-High Slew-Rate Adjustment
Voltage Waveforms: Low-to-High Slew-Rate Adjustment
Load Circuit: Error Output Measurements
Voltage Waveforms: Open Drain Output Low-to-High
Transition Time (with respect to RESET input)
Voltage Waveforms: Open Drain Output High-to-Low
Transition Time (with respect to clock inputs)
Voltage Waveforms: Open Drain Output Low-to-High
Transition Time (with respect to clock inputs)
NOTES:
1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR
≤
10MHz, Zo = 50
Ω
, input
slew rate = 1 V/ns ±20% (unless otherwise specified).
C
L
= 10 pF
R
L
= 50
Ω
DUT
Out
Test Point
V
DD
V
OH
80%
20%
V
OL
Output
dv_f
dt_f
C
L
= 10 pF
R
L
= 50
Ω
DUT
Out
Test Point
V
OL
20%
80%
V
OH
Output
dv_r
dt_r
C
L
= 10 pF
R
L
= 1K
Ω
DUT
Out
Test Point
V
DD
V
OH
V
CC
Output
Waveform 2
LVCMOS
RESET
Input
t
PLH
V
CC
/2
0.15V
0V
0V
V
CC
V
ICR
t
HL
Timing
Inputs
V
ICR
V
I(PP)
Output
Waveform 1
V
CC
/2
V
OL
V
OH
Output
Waveform 2
0.15V
0V
V
ICR
t
HL
Timing
Inputs
V
ICR
V
I(PP)
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