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參數(shù)資料
| 型號： | ICS9FG1901HKLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FREQUENCY GENERATOR 72-QFN |
| 標準包裝： | 1 |
| 系列： | PCI Express® (PCIe) |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | 存儲器，DIMM，PCI Express（PCIe） |
| 輸入： | HCSL |
| 輸出： | HCSL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:19 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 400MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-VFQFPN（10x10） |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 1251 (CN2011-ZH PDF) |
| 其它名稱： | 800-1264-6 |
IDTTM
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
13
Electrical Characteristics - Skew and Differential Jitter Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
Group
Parameter
Description
Min
Typ
Max
Units
Notes
CLK_IN, DIF[x:0]
tSPO_PLL
Input-to-Output Skew in PLL mode (1:1 only),
nominal value @ 25°C, 3.3V
-500
270
500
ps
1,2,4,5,8,
12
CLK_IN, DIF[x:0]
tPD_BYP
Input-to-Output Skew in Bypass mode (1:1 only),
nominal value @ 25°C, 3.3V
2.5
3.8
4.5
ns
1,2,3,5,
12
CLK_IN, DIF [x:0]
tSPO_PLL
Input-to-Output Skew Variation in PLL mode
(over specified voltage / temperature operating ranges)
270
|500|
ps
1,2,4,5,6,
10,12
CLK_IN, DIF [x:0]
tPD_BYP
Input-to-Output Skew Variation in Bypass mode
(over specified voltage / temperature operating ranges)
467
|500|
ps
1,2,3,4,5,
6,10,12
DIF[18:17]
tSKEW_G2
Output-to-Output Skew Group of 2
(Common to Bypass and PLL mode)
10
50
ps
1,2,12
DIF[16:0]
tSKEW_G17
Output-to-Output Skew Group of 17
(Common to Bypass and PLL mode)
70
100
ps
1,2,12
DIF[18:0]
tSKEW_A19
Output-to-Output Skew across all 19 outputs (Common to
Bypass and PLL mode - all outputs at same gear)
70
150
ps
1,2,3,12
DIF[18:0]
tJPH
Differential Phase Jitter (RMS Value)
5
10
ps
1,4,7,12
DIF[18:0]
tSSTERROR
Differential Spread Spectrum Tracking Error (peak to peak)
40
80
ps
1,4,9,12
PLL Jitter Peaking
jpeak-hibw
(HIGH_BW# = 0)
0
2.2
2.5
dB
11,12
PLL Jitter Peaking
jpeak-lobw
(HIGH_BW# = 1)
0
1.4
2
dB
11,12
PLL Bandwidth
pllHIBW
(HIGH_BW# = 0)
2
3.7
4
MHz
12,13
PLL Bandwidth
pllLOBW
(HIGH_BW# = 1)
0.7
1.2
1.4
MHz
12,13
NOTES on Skew and Differential Jitter Parameters:
8. t is the period of the input clock
11. Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking.
12. Guaranteed by design and characterization, not 100% tested in production.
13. Measured at 3 db dow n or half pow er point.
3. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4. This parameter is deterministic for a given device
1. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
2. Measured from differential cross-point to differential cross-point
10. This parameter is an absolute value. It is not a double-sided figure.
9. Differential spread spectrum tracking error is the difference in spread spectrum tracking betw een tw o 9FG1901H devices This parameter is measured at the
outputs of tw o separate 9FG1901H devices driven by a single CK410B+ in Spread Spectrum mode. The 9FG1901H must set to high bandw idth. The spread
spectrum characterisitics are : maximum of 0.5%, 30 to 33KHz modulation frequency, linear profile.
5. Measured with scope averaging on to find mean value.
6. Long-term variation from nominal of input-to-output skew over temperature and voltage for a single device.
7. This parameter is measured at the outputs of two separate 9FG1901H devices driven by a single CK410B+. The 9FG1901H must be set to high bandwidth.
Differential phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including the affects of spread spectrum). Target ranges of
consideration are agents with BW of 1-22MHz and 11-33MHz.
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