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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� ICS9FG1901HKLFT
寤犲晢锛� IDT, Integrated Device Technology Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 17/18闋�(y猫)
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鎻忚堪锛� IC FREQUENCY GENERATOR 72-QFN
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
绯诲垪锛� PCI Express® (PCIe)
椤炲瀷锛� 鏅�(sh铆)閻�/闋荤巼鐧�(f膩)鐢熷櫒
PLL锛� 鏄�
涓昏鐩殑锛� 瀛樺劜(ch菙)鍣�锛孌IMM锛孭CI Express锛圥CIe锛�
杓稿叆锛� HCSL
杓稿嚭锛� HCSL
闆昏矾鏁�(sh霉)锛� 1
姣旂巼 - 杓稿叆:杓稿嚭锛� 1:19
宸垎 - 杓稿叆:杓稿嚭锛� 鏄�/鏄�
闋荤巼 - 鏈€澶э細 400MHz
闆绘簮闆诲锛� 3.135 V ~ 3.465 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 72-VFQFN 瑁搁湶鐒婄洡
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 72-VFQFPN锛�10x10锛�
鍖呰锛� 妯�(bi膩o)婧�(zh菙n)鍖呰
鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 1251 (CN2011-ZH PDF)
鍏跺畠鍚嶇ū锛� 800-1264-6
IDTTM
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
8
SMBusTable: FSB Frequency Select Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
GRSEL_17
Group of 17 gear ratio select
RW
Gear Ratio
1:1
1
Bit 6
GRSEL_2
Group of 2 gear ratio select
RW
Gear Ratio
1:1
1
Bit 5
X
Bit 4
RW
Latch
Bit 3
FSBG_3
FSB Gear Ratio FS_3
RW
x
Bit 2
FSBG_2
FSB Gear Ratio FS_2
RW
0
Bit 1
FSBG_1
FSB Gear Ratio FS_1
RW
x
Bit 0
FSBG_0
FSB Gear Ratio FS_0
RW
1
SMBusTable: Output Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
DIF_7
Output Control
RW
Hi-Z
Enable
1
Bit 6
DIF_6
Output Control
RW
Hi-Z
Enable
1
Bit 5
DIF_5
Output Control
RW
Hi-Z
Enable
1
Bit 4
DIF_4
Output Control
RW
Hi-Z
Enable
1
Bit 3
DIF_3
Output Control
RW
Hi-Z
Enable
1
Bit 2
DIF_2
Output Control
RW
Hi-Z
Enable
1
Bit 1
DIF_1
Output Control
RW
Hi-Z
Enable
1
Bit 0
DIF_0
Output Control
RW
Hi-Z
Enable
1
SMBusTable: Output and PLL BW Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
RW
High BW
Low BW
1
Bit 6
RW
Bypass
PLL
1
Bit 5
DIF_13
Output Control
RW
Hi-Z
Enable
1
Bit 4
DIF_12
Output Control
RW
Hi-Z
Enable
1
Bit 3
DIF_11
Output Control
RW
Hi-Z
Enable
1
Bit 2
DIF_10
Output Control
RW
Hi-Z
Enable
1
Bit 1
DIF_9
Output Control
RW
Hi-Z
Enable
1
Bit 0
DIF_8
Output Control
RW
Hi-Z
Enable
1
Note: Bit 7 is wired OR to the HIGH_BW# input, any 0 selects High BW
Note: Bit 6 is wired OR to the SMB_A2_PLLBYP# input, any 0 selects Fanout Bypass mode
SMBusTable: Output Enable Readback Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
R
X
Bit 6
R
X
Bit 5
R
X
Bit 4
R
X
Bit 3
R
X
Bit 2
R
X
Bit 1
R
X
Bit 0
R
X
Readback
Readback - OE_01234# Input
Readback
Readback - OE5# Input
Readback - OE6# Input
Readback
see note
PLL_BW# adjust
Readback - OE7# Input
-
Byte 1
Byte 0
DIF(16:0)
DIF(18:17)
FS_A_410 Latched Input
-
Reserved
See ICS9FG1901
Programmable Gear Ratios
Table
-
8
72
Readback - OE9# Input
Readback - OE8# Input
see note
BYPASS# test mode / PLL
Byte 3
Byte 2
Readback - HIGH_BW# In
Readback
Readback - SMB_A2_PLLBYP# In
Readback
鐩搁棞(gu膩n)PDF璩囨枡
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鍙冩暩(sh霉)鎻忚堪
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