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參數(shù)資料
| 型號： | ICS950227 |
| 英文描述： | Programmable Timing Control Hub for P4 |
| 中文描述： | 可編程定時控制中心，為小 |
| 文件頁數(shù)： | 15/17頁 |
| 文件大?。?/td> | 128K |
| 代理商： | ICS950227 |
15
Integrated
Circuit
Systems, Inc.
ICS950227
0641D—07/03/03
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined
phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described
below as Tpci.
3V66 & PCI Phase Relationship
3V66 (1:0)
3V66 (4:2)
3V66_5
PCICLK_F (2:0) PCICLK (6:0)
Tpci
PD# Functionality
#
P
O
T
S
_
U
P
C
T
U
P
C
C
U
P
C
6
6
V
3
T
U
O
_
z
H
M
6
6
F
_
K
K
L
L
C
C
I
I
C
P
P
C
K
L
C
I
C
P
T
O
z
D
H
/
B
M
8
S
4
U
1
l
m
r
N
l
m
r
N
z
H
M
6
6
N
I
z
H
M
6
6
N
I
z
H
M
6
6
N
I
z
H
M
6
6
z
H
M
8
4
0
t
M
*
f
t
o
w
o
L
w
o
L
w
o
L
w
o
L
w
o
L
Group Skews at Common Transition Edges
GROUP
3V66
SYMBOL
3V66
CONDITIONS
3V66 (5:0) pin to pin skew
PCI_F (2:0) and
PCI (6:0) pin to pin skew
3V66 (5:0) leads 33MHz PCI
MIN
0
TYP
136
MAX
250
UNITS
ps
PCI
PCI
0
101
500
ps
3V66 to PCI
S
3V66-PCI
1.5
2.08
3.5
ns
1
Guarenteed by design, not 100% tested in production.
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