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參數(shù)資料
| 型號： | ICS9248-95 |
| 英文描述： | Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| 中文描述： | 頻率發(fā)生器 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 310K |
| 代理商： | ICS9248-95 |
9
ICS9248-95
310D—04/12/05
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the
ICS9248-95
. It is used to turn off the PCICLK [4:0] clocks for low power operation.
PCI_STOP# is synchronized by the
ICS9248-95
internally. The minimum that the PCICLK [4:0] clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK [4:0] clocks. PCICLK [4:0] clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK [4:0] clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
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| ICS9248-96 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248-97 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
| ICS9248-98 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
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| ICS9248AF-152T | 制造商:Integrated Device Technology Inc 功能描述:ELECTRONIC COMPONENT |
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