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參數(shù)資料
| 型號： | ICS9248-95 |
| 英文描述： | Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| 中文描述： | 頻率發(fā)生器 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 310K |
| 代理商： | ICS9248-95 |
6
ICS9248-95
310D—04/12/05
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
t
t
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
B
#
n
D
W
X
1
1
1
1
1
1
1
P
n
o
D
0
S
F
d
e
F
_
K
L
)
e
v
R
4
K
L
C
I
C
P
K
L
C
I
C
P
K
L
C
I
C
P
K
L
C
I
C
P
K
L
C
I
C
P
7
6
5
4
3
2
1
0
-
7
-
1
1
1
1
8
#
A
(
h
C
c
L
C
P
(
)
n
I
3
2
1
0
)
)
)
)
)
n
A
n
A
n
A
n
A
n
A
(
(
(
(
(
3
2
1
0
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
t
t
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
B
#
n
D
W
X
1
1
1
1
1
1
1
P
n
o
D
2
S
F
d
e
F
_
K
L
C
)
e
v
R
)
e
v
R
_
M
A
R
D
S
K
L
C
U
P
C
K
L
C
U
P
C
K
L
C
U
P
C
7
6
5
4
3
2
1
0
-
6
-
-
9
2
3
5
#
(
h
c
L
P
C
(
(
4
)
n
A
U
3
4
4
4
)
)
)
)
n
A
n
A
n
A
(
n
A
(
(
(
F
2
1
0
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
t
t
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
B
#
n
D
W
1
1
1
1
1
1
1
1
P
n
o
D
)
v
n
v
A
v
n
v
A
v
n
v
A
v
n
v
A
(
v
n
v
A
(
v
n
v
A
(
v
n
v
A
(
v
n
v
A
(
7
6
5
4
3
2
1
0
7
8
0
1
8
9
1
2
1
1
2
2
2
2
3
3
(
(
1
0
1
1
9
8
7
6
5
4
M
M
M
M
M
M
M
M
A
A
A
A
A
A
A
A
R
R
R
R
R
R
R
R
D
D
D
D
D
D
D
D
S
S
S
S
S
S
S
S
)
)
)
)
)
)
)
(
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