參數(shù)資料
型號(hào): ICS8S89834AKILF
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 10/17頁(yè)
文件大小: 0K
描述: IC CLOCK MUX 2:4 1GHZ 16-VFQFN
標(biāo)準(zhǔn)包裝: 100
系列: HiPerClockS™
類型: 多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 2:4
差分 - 輸入:輸出: 無(wú)/是
輸入: LVCMOS,LVTTL
輸出: ECL,LVPECL
頻率 - 最大: 1GHz
電源電壓: 2.375 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-VFQFPN(3x3)
包裝: 托盤
ICS8S89834I Data Sheet
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER
ICS8S89834AKI REVISION A FEBRUARY 4, 2010
2
2010 Integrated Device Technology, Inc.
Table 1. Pin Descriptions
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number
Name
Type
Description
1, 2
Q1, nQ1
Output
Differential output pair. LVPECL/ECL interface levels.
3, 4
Q2, nQ2
Output
Differential output pair. LVPECL/ECL interface levels.
5, 6
Q3, nQ3
Output
Differential output pair. LVPECL/ECL interface levels.
7, 14
Vcc
Power
Positive supply pins.
8
EN
Input
Pullup
Synchronizing clock enable. When LOW, Q outputs will go LOW and nQ outputs will
go HIGH on the next LOW transition at IN inputs. Input threshold is VCC/2V. Includes a
37k
pullup resistor. Default state is HIGH when left floating. The internal latch is
clocked on the falling edge of the input signal IN1, IN2.
LVTTL/LVCMOS interface levels.
9
IN2
Input
Pullup
Single-ended clock input. LVCMOS/LVTTL interface levels.
10
nc
Unused
No connect.
11
SEL
Input
Pullup
Select clock input. When LOW, selects IN2 and when HIGH selects IN1.
LVCMOS/LVTTL interface levels.
12
IN1
Input
Pullup
Single-ended clock input. LVCMOS/LVTTL interface levels.
13
VEE
Power
Negative supply pin.
15, 16
Q0, nQ0
Output
Differential output pair. LVPECL/ECL interface levels.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
RPULLUP
Input Pullup Resistor
37
k
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