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參數(shù)資料
| 型號： | ICS8536AG-02LF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER MUX 3:6 24-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 62 |
| 系列： | HiPerClockS™ |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:6 |
| 差分 - 輸入:輸出： | 無/是 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | LVPECL |
| 頻率 - 最大： | 266MHz |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
ICS8536AG-02 REVISION A JULY 21, 2010
6
2010 Integrated Device Technology, Inc.
ICS8536-02 Data Sheet
1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
AC Electrical Characteristics
Table 6A. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at fOUT unless noted otherwise.
NOTE 1: Measured from VCC/2 of the input crossing point to the differential output crossing point.
NOTE 2: Driving CLK0 input.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 6: Measured on either XTAL0 or XTAL1 when single-ended CLK0 switching at 150MHz or 250MHz.
Table 6B. AC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at fOUT unless noted otherwise.
NOTE 1: Measured from VCC/2 of the input crossing point to the differential output crossing point.
NOTE 2: Driving CLK0 input.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 6: Measured on either XTAL0 or XTAL1 when single-ended CLK0 switching at 150MHz or 250MHz.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
266
MHz
tPD
Propagation Delay; NOTE 1
1.35
1.85
ns
tjit
Buffer Additive Phase Jitter, RMS;
NOTE 2
155.52MHz, Integration Range:
12kHz – 20MHz
0.149
ps
tsk(o)
Output skew; NOTE 3, 4
55
ps
tsk(pp)
Part-to-Part skew; NOTE 4, 5
500
ps
tR / tF
Output Rise/Fall Time
20% to 80%
200
700
ps
odc
Output Duty Cycle
47
53
%
MUX_ISOLATION MUX Isolation; NOTE 6
= 150MHz
48
dB
= 250MHz
45
dB
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
266
MHz
tPD
Propagation Delay; NOTE 1
1.4
1.9
ns
tjit
Buffer Additive Phase Jitter, RMS;
NOTE 2
155.52MHz, Integration Range:
12kHz – 20MHz
0.149
ps
tsk(o)
Output skew; NOTE 3, 4
55
ps
tsk(pp)
Part-to-Part skew; NOTE 4, 5
500
ps
tR / tF
Output Rise/Fall Time
20% to 80%
200
700
ps
odc
Output Duty Cycle
47
53
%
MUX_ISOLATION MUX Isolation; NOTE 6
= 150MHz
40
dB
= 250MHz
40
dB
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