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參數(shù)資料
| 型號(hào)： | ICS8430-51 |
| 英文描述： | 600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| 中文描述： | 600MHz的，低抖動(dòng)的LVCMOS / LVTTL至3.3伏的LVPECL頻率合成器 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 147K |
| 代理商： | ICS8430-51 |
8430AY-51
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 11, 2003
10
PRELIMINARY
ICS8430-51
600MH
Z
, L
OW
J
ITTER
LVCMOS/LVTTL-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
5B. LVPECL O
UTPUT
T
ERMINATION
3.3V
F
OUT
F
IN
5
2Z
o
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o
= 50
Z
o
= 50
Z
o
= 50
Z
o
= 50
F
IGURE
5A. LVPECL O
UTPUT
T
ERMINATION
RTT =
1
(V
OH
+ V
OL
/ V
CC
–2) –2
Z
o
Z
o
= 50
Z
o
= 50
50
50
RTT
V
CC
- 2V
F
IN
F
OUT
Z
o
= 50
Z
o
= 50
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 5A and 5Bshow two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
LVPECL O
UTPUTS
The schematic of the ICS8430-51 layout example used in
this layout guideline is shown in Figure 6A. The ICS8430-51
recommended PCB board layout for this example is shown
in Figure 6B. This layout example is used as a general guide-
L
AYOUT
G
UIDELINE
F
IGURE
6A. S
CHEMATIC
OF
R
ECOMMENDED
L
AYOUT
TL2
Zo = 50 Ohm
X1
R1
125
Termination
B (Not shown
in the layout)
S_LOAD
S_DATA
U1
8430-01
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
17
18
19
20
21
22
23
24
3
3
3
2
2
2
2
2
M5
M6
M7
M8
N0
N1
N2
GND
T
V
F
n
V
F
n
G
MR
S_CLOCK
SVCCA
nXREF_IN
XTAL1
M
M
M
M
M
V
n
X
IN-
R1
50
V
F
C15
0.1u
T
S_CLOCK
MR
C11
0.01u
R7
10
C14
0.1u
F
VDD
R3
125
V
R4
84
IN+
Termination A
VDD
IN-
TL1
Zo = 50 Ohm
R2
50
REF_IN
XTAL_SEL
C16
22u
R3
50
R2
84
IN+
line. The layout in the actual system will depend on the
selected component types, the density of the components,
the density of the traces, and the stack up of the P.C. board.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS8430AY-51 | 600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430AY-51T | 600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430-61 | 500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS8430AYI-61 | 500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS8430AYI-61T | 500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS843051AG | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR |
| ICS843051AGLF | 功能描述:IC CLK GEN GIG ETH LVPECL 8TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ICS843051AGLFT | 功能描述:IC CLOCK GENERATOR LVPECL 8TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS843051AGT | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR |
| ICS8430-61 | 制造商:ICS 制造商全稱:ICS 功能描述:500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
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