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參數(shù)資料
| 型號： | ICS307 |
| 英文描述： | RES, 47 5%, 1206 |
| 中文描述： | 串行可編程時鐘源 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 107K |
| 代理商： | ICS307 |
ICS307
Serially Programmable Clock Source
MDS 307 D
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126(408) 295-9800tel www.icst.com
5
Revision 042501
MSB
LSB
R6:R0
V8:V0
S2:S0
F1:F0
TTL
C1:C0
Reference Divider Word (RDW)
VCO Divider Word (VDW)
Output Divider Select (OD)
Function of CLK2 Output
Duty Cycle Setting
Internal Load Capacitance for Crystal
MSB
LSB
MSB
LSB
C1 C0
TTL
F1
F0
S2
S1
S0
Configuring the ICS307
The ICS307 can be programmed to set the output functions and frequencies. The three data bytes are
written to the DATA pin, in this order:
V8 V7 V6 V5 V4 V3 V2 V1
V0 R6 R5 R4 R3 R2 R1 R0
C1 is loaded into the port first and R0 last.
Programming Example
To generate 66.66 MHz from a 14.31818 MHz input, the RDW should be 59, the VDW should be 276,
and the Output Divide is 2. Selecting the minimum internal load capacitance, CMOS duty cycle, and CLK2
to be OFF means that the following three bytes are sent to the ICS307:
00110001
Byte 1
10001010
Byte 2
00111011
Byte 3
As shown in Figure 2, after these 24 bits are clocked into the ICS307, taking STROBE high will send this data
to the internal latch, and the CLK output will lock within 10 ms.
NOTE: If STROBE is in the high state and SCLK is pulsed, DATA is clocked directly to the internal latch
and the output conditions will change accordingly. Although this will not damage the ICS307, it is
recommended that STROBE be kept low while DATA is being clocked into the ICS307 in order to avoid
unintended changes on the output clocks.
Power up default values for ICS 307-02
0
0
1
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
The input frequency will come from both outputs.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS307-01 | 制造商:ICS 制造商全稱:ICS 功能描述:SERIALLY PROGRAMMABLE CLOCK SOURCE |
| ICS307-02 | 制造商:ICS 制造商全稱:ICS 功能描述:SERIALLY PROGRAMMABLE CLOCK SOURCE |
| ICS307-03 | 制造商:ICS 制造商全稱:ICS 功能描述:SERIALLY PROGRAMMABLE CLOCK SOURCE |
| ICS307G-03 | 功能描述:IC SRL PROGR CLK SOURCE 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ II 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS307G-03LF | 功能描述:IC CLK SOURCE SRL PROGR 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ II 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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