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參數(shù)資料
| 型號： | ICS307 |
| 英文描述： | RES, 47 5%, 1206 |
| 中文描述： | 串行可編程時鐘源 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 107K |
| 代理商： | ICS307 |
ICS307
Serially Programmable Clock Source
MDS 307 D
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126(408) 295-9800tel www.icst.com
3
Revision 042501
Determining the Output Frequency
On power-up the ICS307-01 on-chip registers can have random values, so almost any frequency may be
output from the part. CLK1 will always have some clock signal present, but CLK2 could possibly be OFF
(low).
The ICS307-02 on-chip registers are initially configured to provide a x1 output clock on both the CLK1
and CLK2 outputs. The output frequency will be the same as the input clock or crystal. This is useful if
the ICS307 will provide the initial system clock at power-up. Since this feature is an advantage in most
systems, the ICS307-02 is recommended for new designs.
With programming, the user has full control in changing the desired output frequency to any value over the
range shown in Table 1 on page 4. The output of the ICS307 can be determined by the following simple
equation:
To determine the best combination of VCO, reference, and output dividers, contact ICS application
engineering. You may also fax this page to ICS at 408 295 9818(fax). Be sure to indicate the following:
Your Name ________________ Company Name___________________ Telephone_________________
Respond by e-mail (list your e-mail address) __________________or fax number ___________________
Desired input crystal_______ or clock_______ (in MHz) Desired output frequency_______________
REF Output_______VDD = 3.3V or 5V _______ Duty Cycle: 40-60% _____ or 45-55% required____
CLK1 frequency = Input frequency 2 (VDW+8)
(RDW+2)(OD)
Also, the following operating ranges should be observed:
55 MHz < Input frequency 2 (VDW+8)
(RDW+2)
< 400 MHz
200 kHz < Input Frequency
(RDW+2)
Where
VCO Divider Word (VDW) = 4 to 511 (0, 1, 2, 3 are not permitted)
Reference Divider Word (RDW) = 1 to 127 (0 is not permitted)
Output Divider = values on page 4
Commercial temperature range.
Industrial temperature limits are
60 MHz to 360 MHz.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS307-01 | 制造商:ICS 制造商全稱:ICS 功能描述:SERIALLY PROGRAMMABLE CLOCK SOURCE |
| ICS307-02 | 制造商:ICS 制造商全稱:ICS 功能描述:SERIALLY PROGRAMMABLE CLOCK SOURCE |
| ICS307-03 | 制造商:ICS 制造商全稱:ICS 功能描述:SERIALLY PROGRAMMABLE CLOCK SOURCE |
| ICS307G-03 | 功能描述:IC SRL PROGR CLK SOURCE 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ II 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS307G-03LF | 功能描述:IC CLK SOURCE SRL PROGR 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ II 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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