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參數(shù)資料
| 型號(hào)： | ICS2572N |
| 英文描述： | User-Programmable Dual High-Performance Clock Generator |
| 中文描述： | 用戶可編程雙路高性能時(shí)鐘發(fā)生器 |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 144K |
| 代理商： | ICS2572N |
Digital Inputs
The FS0-FS3 pins and the STROBE pin are used to select the
desired operating frequency of the VCLK output from the 16
pre-programmed/user-programmed selections in the ICS2572.
These pins are also used to load new frequency data into the
registers.
Available configurations for the STROBE input include: posi-
tive-edge triggered, negative-edge triggered, high-level trans-
parent, and low-level transparent (see Ordering Information).
VCLK Output Frequency Selection
To change the VCLK output frequency, simply write the ap-
propriate data to the ICS2572 FS inputs. Do not perform any
further writes to the device for 50 milliseconds (assumes a
14.318 MHz reference). The synthesizer will output the new
frequency programmed into that location after a brief delay
(see timeout specifications).
MCLK Output Frequency Selection
The MS0-MS1 pins are used to directly select the desired
operating frequency of the MCLK output from the four pre-
programmed/user-programmed selections in the ICS2572.
These inputs are not latched, nor are they involved with mem-
ory programming operations.
Programming Mode Selection
A programming sequence is defined as a period of at least 50
milliseconds of no data writes to the ICS2572 (to clear the shift
register) followed by a series of data writes (as shown here):
FS0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FS1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FS2
FS3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
START
bit (must be “0”)
”
R/W*
control
”
L0
(location LSB)
”
L1
”
L2
”
L3
”
L4
(location MSB)
”
N0
(feedback LSB)
”
N1
”
N2
”
N3
”
N4
”
N5
”
N6
”
N7
(feedback MSB)
”
EXTFREQ
bit (selected if “1”)
”
D0
(post-divider LSB)
”
D1
(post-divider MSB)
”
STOP1
bit (must be “1”
”
STOP2
bit (must be “1”)
”
ICS2572
E-97
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS2595M-S04 | Video/Graphics Clock Generator |
| ICS2595N-S02 | Video/Graphics Clock Generator |
| ICS2595N-S04 | Video/Graphics Clock Generator |
| ICS2572M-A01 | Peripheral IC |
| ICS2572M-AXX | Peripheral IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS2572N-A01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| ICS2572N-AXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| ICS2572N-B01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| ICS2572N-BXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| ICS2572N-C01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
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