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參數(shù)資料
| 型號(hào)： | ICS2510CGT-CQ0 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DVR PLL 3.3V 24-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘驅(qū)動(dòng)器，扇出配送，擴(kuò)展頻譜時(shí)鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 175MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 2510CGT-CQ0 |
2
ICS2510C
0010G—09/22/09
Pin Descriptions
Note:
1.
Weak pull-ups on these inputs
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
AGND
PWR
Analog Ground
2, 10, 14
VCC
PWR
Power Supply (3.3V)
3
CLK0
OUT
Buffered clock output.
4
CLK1
OUT
Buffered clock output.
5
CLK2
OUT
Buffered clock output.
6, 7, 18, 19
GND
PWR
Ground
8
CLK3
OUT
Buffered clock output.
9
CLK4
OUT
Buffered clock output.
11
OE
1
IN
Output enable (has internal pull_up). When high, normal operation.
When low, clock outputs are disabled to a logic low state.
12
FBOUT
OUT
Feedback output
13
FBIN
IN
Feedback input
15
CLK5
OUT
Buffered clock output.
16
CLK6
OUT
Buffered clock output.
17
CLK7
OUT
Buffered clock output.
20
CLK8
OUT
Buffered clock output.
21
CLK9
OUT
Buffered clock output.
22
VCC
PWR
Power Supply (3.3V) digital supply.
23
AVCC
IN
Analog power supply (3.3V). When input is ground PLL is off and
bypassed.
24
CLKIN
IN
Clock input
Functionality
OE
AVCC
CLK (9:0)
FBOUT
Source
03.33
0
Driven
PLL
N
13.33
Driven
PLL
N
00
0
Driven
CLKIN
Y
1
0
Driven
CLKIN
Y
Test mode:
When AVCC is 0, shuts off the PLL
and connects the input directly to the output buffers
Buffer Mode
INPUTS
OUTPUTS
PLL
Shutdown
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