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參數(shù)資料
| 型號： | ICS2510CGT-CQ0 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DVR PLL 3.3V 24-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時鐘驅(qū)動器，扇出配送，擴(kuò)展頻譜時鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | 時鐘 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 175MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 2510CGT-CQ0 |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS2510C
0010G—09/22/09
Block Diagram
3.3V Phase-Lock Loop Clock Driver
Pin Configuration
The ICS2510C is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology to
align, in both phase and frequency, the CLKIN signal with
the CLKOUT signal. It is specifically designed for use with
synchronous SDRAMs.The ICS2510C operates at 3.3V
VCC and drives up to ten clock loads.
One bank of ten outputs provide low-skew, low-jitter
copies of CLKIN. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLKIN.
Outputs can be enabled or disabled via control (OE)
inputs. When the OE inputs are high, the outputs align in
phase and frequency with CLKIN; when the OE inputs are
low, the outputs are disabled to the logic low state.
The ICS2510C does not require
external RC filter
components.The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.The
test mode shuts off the PLL and connects the input
directly to the output buffer.This test mode, the ICS2510C
can be use as low skew fanout clock buffer device. The
ICS2510C comes in 24 pin 173mil Thin Shrink Small-
Outline package (TSSOP) package.
Meets or exceeds PC133 registered DIMM
specification1.1
Spread Spectrum Clock Compatible
Distributes one clock input to one bank of ten outputs
Operating frequency 25MHz to 175MHz
External feedback input (FBIN) terminal is used to
synchrionize the outputs to the clock input
No external RC network required
Operates at 3.3V Vcc
Plastic 24-pin 173mil TSSOP package
24 Pin TSSOP
4.40 mm. Body, 0.65 mm. pitch
PLL
AVCC
FBIN
CLKIN
CLK0
CLK9
CLK8
CLK7
CLK6
CLK5
CLK4
CLK3
CLK2
CLK1
FBOUT
OE
CLKIN
AVCC
VCC
CLK9
CLK8
GND
CLK7
CLK6
CLK5
VCC
FBIN
AGND
VCC
CLK0
CLK1
CLK2
GND
CLK3
CLK4
VCC
OE
FBOUT
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
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