- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360744 > ICS1889 100Base-FX Integrated PHYceiverTM PDF資料下載
參數(shù)資料
| 型號： | ICS1889 |
| 英文描述： | 100Base-FX Integrated PHYceiverTM |
| 中文描述： | 100Base - FX光纖綜合PHYceiverTM |
| 文件頁數(shù)： | 18/35頁 |
| 文件大?。?/td> | 1096K |
| 代理商： | ICS1889 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁
18
ICS1889
Pin Definitions
MII Interface Pin Descriptions
Transmit Clock TXCLK
The Transmit Clock (TXCLK) is a continuous clock signal
generated by the
ICS1889
to synchronize the Transmit
Enable, Transmit Data and Transmit Error lines. The
ICS1889
clock frequency is 25% of the nominal transmit data
rate. At 100 Mbps its frequency is 25 MHz. The TXCLK
clock duty cycle is in the range 35% to 65%.
Transmit Enable TXEN
Transmit Enable (TXEN) indicates to the
ICS1889
that the
MAC is sending valid data nibbles for transmission on the
physical media. Synchronous with its assertion the
ICS1889
will begin reading the data nibbles on the transmit data lines.
It is the responsibility of the MAC to order the nibbles so that
the preamble is sent first, followed by destination, source,
length, data and CFS fields since the
ICS1889
has no
knowledge of the frame structure and is merely a nibble
processor. The
ICS1889
terminates transmission of nibbles
following the deassertion of Transmit Enable (TXEN).
Transmit Data 3 TXD3
Transmit Data 3 (TXD3) is the most significant bit of the
transmit data nibble. TXD3 is sampled by the
ICS1889
synchronously with the Transmit Data Clock when TXEN is
asserted. When TXEN is de-asserted the
ICS1889
is
unaffected by the state of TXD3
Transmit Data 2 TXD2
Transmit Data 2 (TXD2) is sampled by the
ICS1889
synchronously with the Transmit Data Clock when TXEN is
asserted. When TXEN is de-asserted the
ICS1889
is
unaffected by the state of TXD2.
Transmit Data 1 TXD1
Transmit Data 1 (TXD1) is sampled by the
ICS1889
synchronously with the Transmit Data Clock when TXEN is
asserted. When TXEN is de-asserted the
ICS1889
is
unaffected by the state of TXD1.
Signal
TXCLK
TXEN
TXD3
TXD2
TXD1
TXD0
TXER
RXCLK
RXDV
RXD3
RXD2
RXD1
RXD0
RXER
CRS
COL
Meaning
Signal
TX+
TX–
IPRG
RX+
RX–
REF+
REF–
SD+
SD–
Meaning
Transmit Clock
Transmit Enable
Transmit Data 3
Transmit Data 2
Transmit Data 1
Transmit Data 0
Transmit Error
Receive Clock
Receive Data Valid
Receive Data 3
Receive Data 2
Receive Data 1
Receive Data 0
Receive Error
Carrier Sense
Collision Detect
Transmitted data positive
Transmitted Data negative
Current program
Receive Data positive
Receive Data negative
Frequency reference
Frequency reference
Signal Detect
Signal Detect
SYSR
PRIO
DPEN
LSTA
P4RD
P3TD
P2LI
P1CL
P0FD
NOD/REP
System reset
Priority
Duplex Enable
Link Status
Receive data LED
Transmit data LED
Link Integrity LED
Collision detect LED
Full duplex LED
Node or Repeater Mode Selection
MDC
MDIO
Management Data Clock
Management Data Input/Output
相關PDF資料 |
PDF描述 |
|---|---|
| ICS1892 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-10 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893AF | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1890 | 制造商:ICS 制造商全稱:ICS 功能描述:Auto-Negotiation Advertisement Register (register 4 [0x04]) |
| ICS1890Y | 制造商:ICS 功能描述: 制造商:ICS 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:ICS 功能描述:1890Y-4 制造商:Integrated Device Technology Inc 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| ICS1890Y-14 | 制造商:ICS 制造商全稱:ICS 功能描述:Auto-Negotiation Advertisement Register (register 4 [0x04]) |
| ICS1890Y-4 | 制造商:ICS 功能描述:1890Y-4 |
| ICS1891 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復。