
14
ICS1889
Extended Control Register (register 16)
The Extended Control Register is a 16-bit read write register
used to pre-program the
ICS1889
. At power-up and reset, this
register will be loaded to the default values specified. It may
subsequently be read or written. If written, the result is bit
dependent as discussed below.
Command Register Override (bit 15)
If set to a logic one, this bit allows a subsequent write to the
Status Register (register 1) and the PHY identifier registers 2
and 3. The contents of registers 2 and 3 may be set to any
value. The Status Register may have certain specified bits set
or reset. The first write to registers 1, 2 or 3 after this bit is set
will reset it preventing subsequent writes from having any
effect.
Reserved (bit 14)
This bit is reserved for ICS use. It must always be written with
a logic zero. The value of this bit when read is unspecified and
may be a logic zero or one.
Reserved (bit 13)
This bit is reserved for ICS use. It must always be written with
a logic zero. The value of this bit, when read, is unspecified
and may be a logic zero or one.
Extended Control Register (register 16)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Definition
When bit = 0
When bit = 1
Allow write
Access
RW
RW/0
RW/0
RW/0
RW/0
CW
CW
CW
CW
CW
RW/0
RW
RW
RW
RW/0
RW/0
Default
0
—
—
—
—
P4RD
P3TD
P2LI
P1CL
P0FD
—
1
0
0
—
—
Command Register Override Don’t allow write
Reserved for ICS
Reserved for ICS
Reserved for ICS
Reserved for ICS
PHY address - S4
PHY address - S3
PHY address - S2
PHY address - S1
PHY address - S0
Reserved for ICS
Far End Fault
Transmit Far End Fault
Invalid Error Code Test
Reserved for ICS
Reserved for ICS
Write logic zero. Read unspecified.
Write logic zero. Read unspecified.
Write logic zero. Read unspecified.
Write logic zero. Read unspecified.
MII management
Register address code
0 - 31 Read Only
Write logic zero. Read unspecified.
Disabled
No fault transmitted
Disabled
Write logic zero. Read unspecified.
Write logic zero. Read unspecified.
Enabled
Fault transmitted
Enabled
Reserved (bit 12)
This bit is reserved for ICS use. It must always be written with
a logic zero. The value of this bit when read is unspecified and
may be a logic zero or one.
Reserved (bit 11)
This bit is reserved for ICS use. It must always be written with
a logic zero. The value of this bit when read is unspecified and
may be a logic zero or one.
PHY Address (Bits 10 through 6)
These 5 bits are used to indicate the address of the
ICS1889
on the management port of the MII (any number in the range
0 - 31). A read returns the address. Extra care should be taken
if a command override write is performed on these bits, as a
change in the PHY address must be accounted for by the
device reading and writing to the MII Management interface.
Reserved (bit 5)
This bit is reserved for ICS use. It must always be written with
a logic zero. The value of this bit when read is unspecified and
may be a logic zero or one.