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參數(shù)資料
| 型號(hào)： | I90135 |
| 廠商： | Integrated telecom express,Inc. |
| 英文描述： | ADSL Digital Chip |
| 中文描述： | 寬帶數(shù)字芯片 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 89K |
| 代理商： | I90135 |
Integrated Telecom Express, Inc.
5
I90135
Product Data Sheet
Version 1.2 (June 1999)
Mapper/ Demapper, Monitor, Trellis
Coding, FEQ Update
The demapper converts the constellation
points computed by the FFT to a block of
bits. This essentially consists in identifying
a point in a 2D QAM constellation plane.
The demapper supports trellis coded
demodulation and provides a Viterbi
maximum likelihood estimator. When the
trellis is active, the demapper receives an
indication for the most likely constellation
subset to be used. In the transmit
direction, the mapper performs the inverse
operation, mapping a block of bits into one
constellation point (in a complex x+jy
representation) which is passed to the IFFT
block. The Trellis Encoder generates
redundant bits to improve the robustness of
the transmission, using a 4-Dimensional
Trellis Coded Modulation scheme. The
Monitor computes error parameters for
carriers specified in the Demapper process.
Those parameters can be used for updates
of adaptive filters coefficient, clock phase
adjustments, error detection, etc. A series
of values is constantly monitored, such as
signal power, pilot phase deviations, symbol
erasures generation, loss of frame, etc.
Pin Diagram
VSS
AD_0
AD_1
AD_2
VDD
AD_3
AD_4
VSS
AD_5
AD_6
VDD
AD_7
AD_8
AD_9
VSS
AD_10
AD_11
VDD
AD_12
VSS
PCLK
VDD
AD_13
AD_14
AD_15
VSS
BE1
ALE
VDD
CSB
WR_RDB
RDYB
OBC_TYPE
INTB
RESETB
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101 SLT_FRAME_F
100
SLAP_CLOCK
99
SLR_VAL_F
98
SLR_DAT_F0
97
SLR_DAT_F1
96
SLR_VAL_S
95
94
SLR_DAT_S0
93
SLR_DAT_S1
92 SLR_FRAME_S
91
90 SLR_FRAME_F
89
U_TX_ADDR_0
88
U_TX_ADDR_1
87
U_TX_ADDR_2
86
85
U_TX_ADDR_3
84
U_TX_ADDR_4
83
U_TX_DATA_0
82
U_TX_DATA_1
81
80
U_TX_DATA_2
79
U_TX_DATA_3
78
U_TX_DATA_4
77
U_TX_DATA_5
76
75
U_TX_DATA_6
74
U_TX_DATA_7
73
VDD
SLT_REQ_F
SLT_DAT_S0
SLT_DAT_S1
SLT_DAT_F0
SLT_DAT_F1
VSS
VDD
VSS
VDD
VDD
VDD
VSS
V
1
A
1
A
1
V
1
A
1
A
1
I
1
V
1
A
1
A
1
V
1
A
1
A
1
V
1
C
1
M
1
C
1
V
1
A
1
A
1
A
1
A
1
V
1
P
1
G
1
T
1
T
1
V
1
T
1
V
1
T
1
T
1
T
1
S
S
1
V
1
3
V
3
U
3
U
4
V
4
U
4
U
4
V
4
U
4
U
4
V
4
U
4
U
4
V
5
U
5
U
5
U
5
U
5
V
5
U
5
G
5
V
5
G
5
V
6
U
6
U
6
V
6
U
6
U
6
U
6
U
6
V
6
U
6
U
7
U
7
U
7
V
AFE
TEST
SLAP
UTOPIA
OBC
Figure 3: Pinout (Topside View)
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