參數(shù)資料
型號(hào)： I90135
廠商： Integrated telecom express,Inc.
英文描述： ADSL Digital Chip
中文描述： 寬帶數(shù)字芯片
文件頁(yè)數(shù)： 3/9頁(yè)
文件大?。?/td> 89K
代理商： I90135
Integrated Telecom Express, Inc.
3
I90135
Product Data Sheet
Version 1.2 (June 1999)
Block Diagram
Introduction
The following essential describes the
sequence of actions for the receive
direction, corresponding functions for the
transmit direction are readily derived.
DSP Front End
The DSP front end contains four parts in
the receive direction: the input selector, the
analog front end interface, the decimator
and the time equalizer. The input selector
is used internally to enable test loopbacks
inside the chip. The analog front end
interface transfers 16-bit word, multiplexed
on four input/output signals. As a result,
four dock cycles are needed to transfer one
word. The decimator receives the 16-bit
samples at 8.8 MHz (as sent by the analog
front end chip) and reduces this rate to 2.2
MHz.
Test
Module
Data Symbol Timing Unit
VCXO
DSP
Front-end
FFT/
IFFT
Rotor
Trellis
Coding
Mapper/
Demapper
Generic
TC
Reed/
Solomon
ATM
Specific
TC
Reset
Controller Interface
I
Clock
Test Signals
AFE
Interface
SLAP
Utopia
Reset
Controller Bus
General Purpose I/Os
Figure 2: I90135 Block Diagram
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