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| 型號(hào)： | I90135 |
| 廠商： | Integrated telecom express,Inc. |
| 英文描述： | ADSL Digital Chip |
| 中文描述： | 寬帶數(shù)字芯片 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 89K |
| 代理商： | I90135 |
Integrated Telecom Express, Inc.
4
I90135
Product Data Sheet
Version 1.2 (June 1999)
The Tme Equalizer (TEQ) module is an FIR
filter with programmable coefficients. Its
main purpose is to reduce the effect of
Inter-Symbol Interferences (ISI) by
shortening the channel impulse response.
Both the decimator and TEQ can be
bypassed.
In the transmit direction, the DSP front end
includes: sidelobe filtering, clipping, delay
equalization, and interpolation. The
sidelobe filtering and delay equalization are
implemented by IIR filters, reducing the
effect of echo in FDM systems.
Clipping is a statistical process limiting the
amplitude of the output signal, optimizing
the dynamic range of the AFE.
The interpolator receives data at 2.2 MHz
and generates samples at a rate of 8.8 MHz.
DMT Modem
This computational module is a
programmable DSP unit. Its instruction set
enables functions like FFT, IFFT, scaling,
rotor, and Frequency Equalization (FEQ).
This block implements the core of the DMT
algorithm as specified in ANSI T1.413.
In the RX path, the 51 2-point FFT
transforms the time domain DMT symbol
into a frequency domain representation,
which can be further decoded by the
subsequent demapping stages. After the
first stage time domain equalization and
FFT block an essentially ICI (InterCarrier
Interferences)-free carrier information
stream has been obtained. This stream is
still affected by carrier-specific channel
distortion resulting in an attenuation of the
signal amplitude and a rotation of the signal
phase. To compensate for these effects,
the FFT is followed by a Frequency Domain
Equalizer (FEQ) and a rotor (phase shifter).
In the TX path, the IFFT transforms the
DMT symbol generated in the frequency
domain by the mapper into a time domain
representation. The IFFT block is proceed
by a fne tune gain and a rotor stage,
allowing for a compensation of the possible
frequency mismatch between the master
clock frequency and the transmitter clock
frequency (which may be locked to another
reference). The FFT module is a slave DSP
engine controlled by the transceiver
controller. It works off line and
communicates with the other blocks via
buffers controlled by the DSTU block. The
DSP executes a program stored in a RAM
area, a very
flexible implementation open
for future enhancements.
DPLL
The Digital PLL module receives a metric for
the phase error of the pilot tone. In
general, the clock frequencies at the
transmitter and receiver do not match
exactly. The phase error is filtered and
integrated by a low pass filter, yielding an
estimation of the frequency offset. Various
processes can use this estimate to deal with
the frequency mismatch. In particular,
small accumulated phase error can be
compensated in the frequency domain by a
rotation of the received code constellation
(Rotor). Larger errors are compensated in
the time domain by inserting or deleting
clock cycles in the sample input sequence.
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