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參數(shù)資料
| 型號(hào)： | I5116X |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 音頻合成 |
| 英文描述： | SINGLE-CHIP 1 TO 16 MINUTES DURATION VOICE RECORD/PLAYBACK DEVICES WITH DIGITAL STORAGE CAPABILITY |
| 中文描述： | 960 SEC, SPEECH SYNTHESIZER WITH RCDG, UUC25 |
| 封裝： | DIE-25 |
| 文件頁數(shù)： | 71/88頁 |
| 文件大小： | 612K |
| 代理商： | I5116X |
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ISD5100 – SERIES
Publication Release Date: October, 2003
- 71 -
Revision 0.2
Acknowledge
The number of data bytes transferred between the start and stop conditions from transmitter to
receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is
a HIGH level signal put on the interface bus by the transmitter during which time the master generates
an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. In addition, a master receiver must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so
that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-
up and hold times must be taken into consideration). A master receiver must signal an end of data to
the transmitter by not generating an acknowledge on the last byte that has been clocked out of the
slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a
stop condition.
START
condition
Example of an I
2
C-bus configuration using two microcontrollers
SDA
SCL
MICRO-
CONTROLLER
LCD
DRIVER
STATIC
RAM OR
EEPROM
GATE
ARRAY
ISD 5116
8
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
not acknowledge
acknowledge
dock pulse for
acknowledgement
S
Acknowledge on the I
2
C-bus
1
2
9
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