參數(shù)資料
型號： I5108S
廠商： WINBOND ELECTRONICS CORP
元件分類： 音頻合成
英文描述： SINGLE-CHIP 1 TO 16 MINUTES DURATION VOICE RECORD/PLAYBACK DEVICES WITH DIGITAL STORAGE CAPABILITY
中文描述： 480 SEC, SPEECH SYNTHESIZER WITH RCDG, PDSO28
封裝： 0.300 INCH, PLASTIC, SOIC-28
文件頁數(shù)： 19/88頁
文件大?。?/td> 612K
代理商： I5108S
ISD5100 – SERIES
Publication Release Date: October, 2003
- 19 -
Revision 0.2
7.3.4. Data Bytes
In the I
2
C write mode, the device can accept data sent after the command byte. If a register load
option is selected, the next two bytes are loaded into the selected register. The format of the data is
MSB first, the I
C standard. Thus to load DATA<15:0> into the device, DATA<15:8> is sent first, the
byte is acknowledged, and DATA<7:0> is sent next. The address register consists of two bytes. The
format of the address is as follows:
ADDRESS<15:0> = PAGE_ADDRESS<10:0>, BLOCK_ADDRESS<4:0>
Note: if an analog function is selected, the block address bits must be set to 00000. Digital
Read and Write are block addressable.
When the device is polled with the Read Status command, it will return three bytes of data. The first
byte is the status byte, the next the upper address byte and the last the lower address byte. The status
register is one byte long and its bit function is:
STATUS<7:0> = EOM, OVF, READY, PD, PRB, DEVICE_ID<2:0>
Lower address byte will always return the block address bits as zero, either in digital or analog mode.
The functions of the bits are:
EOM
BIT 7
Indicates whether an EOM interrupt has occurred.
OVF
BIT 6
Indicates whether an overflow interrupt has occurred.
READY
BIT 5
Indicates the internal status of the device – if READY is LOW
no new commands should be sent to device, i.e. Not Ready.
PD
BIT 4
Device is powered down if PD is HIGH.
PRB
BIT 3
Play/Record mode indicator. HIGH=Play/LOW=Record.
DEVICE_ID
BIT 0, 1, 2
An internal device ID. ISD5116 = 001; ISD5108 = 010;
ISD5104 = 100 and ISD5102 = 101.
It is recommended that you read the status register after a Write or Record operation to ensure that
the device is ready to accept new commands. Depending upon the design and the number of pins
available on the controller, the polling overhead can be reduced. If
INT
and
RAC
are tied to the
microcontroller, it does not have to poll as frequently to determine the status of the ISD5100-SERIES.
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