參數(shù)資料
型號(hào)： HYS72D128500HR-7-B
廠商： INFINEON TECHNOLOGIES AG
英文描述： 184-Pin Registered Double Data Rate SDRAM Module
中文描述： 184針注冊(cè)雙倍數(shù)據(jù)速率SDRAM模塊
文件頁(yè)數(shù)： 23/45頁(yè)
文件大小： 1208K
代理商： HYS72D128500HR-7-B
Registered Double Data Rate SDRAM Module
Electrical Characteristics
23
Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Data Sheet
Address and control input hold time
t
IH
0.9
—
0.9
—
ns
fast slew
rate
3)4)5)6)10)
1.0
—
1.0
—
ns
slow slew
rate
3)4)5)6)10)
Read preamble
Read postamble
Active to Precharge command
Active to Active/Auto-refresh command period
Auto-refresh to Active/Auto-refresh command
period
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B command
Write recovery time
Auto precharge write recovery + precharge time
t
DAL
t
RPRE
t
RPST
t
RAS
t
RC
t
RFC
0.9
0.40
45
65
75
1.1
0.60
120E+3 45
—
—
0.9
0.40
1.1
0.60
120E+3 ns
—
—
t
CK
t
CK
2)3)4)5)
2)3)4)5)
2)3)4)5)
65
75
ns
ns
2)3)4)5)
2)3)4)5)
t
RCD
t
RP
t
RAP
t
RRD
t
WR
20
20
20
15
15
—
—
—
—
—
20
20
20
15
15
—
—
—
—
—
ns
ns
ns
ns
ns
t
CK
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
(
t
WR
/
t
CK
) +
(
t
RP
/
t
CK
)
—
—
200
—
(
t
WR
/
t
CK
) +
(
t
RP
/
t
CK
)
—
—
200
—
2)3)4)5)11)
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
t
WTR
t
XSNR
t
XSRD
t
REFI
1
75
1
75
t
CK
ns
t
CK
μ
s
2)3)4)5)
2)3)4)5)
—
7.8
—
7.8
2)3)4)5)
2)3)4)5)12)
1) 0
°
C
≤
T
A
≤
70
°
C
; V
DDQ
= 2.5 V
±
0.2 V,
V
DD
= +2.5 V
±
0.2 V (DDR333);
V
DDQ
= 2.6 V
±
0.1 V,
V
DD
= +2.6 V
±
0.1 V
(DDR400)
2) Input slew rate
≥
1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is
V
REF
. CK/CK slew rate are
≥
1.0 V/ns.
4) Inputs are not recognized as valid until
V
REF
stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
V
TT
.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
t
HZ
and
t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
t
DQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate
≥
1.0 V/ns , slow slew rate
≥
0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between
V
OH(ac)
and
V
OL(ac)
.
Table 13
Parameter
AC Timing - Absolute Specifications –7/–7F
Symbol
–7F
–7
Unit Note/ Test
Condition
1)1)
DDR266
Min.
DDR266A
Min.
Max.
Max.
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