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參數(shù)資料
| 型號(hào)： | HYM4V33100DTYG-75 |
| 英文描述： | x32 SDRAM Module |
| 中文描述： | X32號(hào)，內(nèi)存模塊 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 73K |
| 代理商： | HYM4V33100DTYG-75 |
PC133 SDRAM AIMM
Rev. 0.1/Apr.01
2
HYM4V33100BTWG Series
PIN DESCRIPTION
PIN
P I N N A M E
D E S C R I P T I O N
C K 0 , C K 1
Clock Inputs
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
C K E
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
/ C S
Chip Select
Enables or disables all inputs except CK, CKE and DQM
B A
SDRAM Bank Address
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
A 0 ~ A 1 0
Address
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
/RAS, /CAS, /WE
Row Address Strobe, Column
Address Strobe, Write Enable
/RAS, /CAS and /WE define the operation
Refer function truth table for details
D Q M 0 ~ D Q M 3
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
D Q 0 ~ D Q 3 1
Data Input/Output
Multiplexed data input / output pin
V C C
Power Supply (3.3V)
Power supply for internal circuits and input buffers
V
SS
Ground
Ground
N C
No Connection
No connection
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