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參數(shù)資料
| 型號： | HYE25L128160AC-8 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES |
| 中文描述： | 128 - Mbit同步低功率DRAM在CHIPSIZE套票 |
| 文件頁數(shù)： | 10/50頁 |
| 文件大?。?/td> | 980K |
| 代理商： | HYE25L128160AC-8 |
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HYB/E 25L128160AC
128-MBit Mobile-RAM
INFINEON Technologies
10
2003-02
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When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS
low at a clock timing after a necessary delay,
W
, from the RAS timing. WE is used to define either
a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 133 MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column
addresses are segmented by the burst length and serial data accesses are done within this
boundary. The first column address to be accessed is supplied at the CAS timing and the
subsequent addresses are generated automatically by the programmed burst length and its
sequence. For example, in a burst length of 8 with interleave sequence, if the first address is
‘
2
’
,
then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using the sequential burst type and page length is a
function of the I/O organisation and column addressing. Full page burst operation does not self
terminate once the burst length has been reached. In other words, unlike burst length of 2, 4 and 8,
full page burst continues until it is terminated using another command.
BA1 BA0 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus (Ax)
Mode Register (Mx)
M4
M3
0
0
1
0
0
1
1
1
M1
M0
M2
1
0
0
0
0
1
1
1
0
1
0
0
1
1
0
0
1
1
1
1
1
0
0
0
1*)
0*)
*)BA1 and BA0 must be 1, 0 to select the Extended Mode Register (Vs. the Mode Register)
TCR
PASR
Temperature-Compensated
Self-Refresh:
max.
case temp.
450
700
85 C
15 C
Partial-Array Self Refresh:
banks to be
self-refreshed
all banks
1/2 array (BA1=0)
1/4 array (BA1=0, BA0=0)
Reserved
Reserved
1/8 array
(BA1=BA0=0, RA11=0)
1/16 array
(BA1=BA0=0,
RA11=RA10=0)
Reserved
all have to be set to "0"
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25L128160AC-7.5 | HEX DIE SET,.052/.068/.100/.21 |
| HYE25L128160AC-7.5 | HEX DIE SET,.052/.068/.178/.25 |
| HYE25L128160AC-75 | 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES |
| HYB25L512160AC-75 | 512MBit Mobile-RAM |
| HYB25L512160AC-7.5 | BJAWBMSpecialty DRAMs Mobile-RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYE25L256160AC | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Mobile-RAM |
| HYE25L256160AC-7.5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:BJAWBMSpecialty DRAMs Mobile-RAM |
| HYE25L256160AC-75 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Mobile-RAM |
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