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參數(shù)資料
| 型號： | HYB511000BJL-70 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 1 M x 1-Bit Dynamic RAM Low Power 1 M ⅴ 1-Bit Dynamic RAM |
| 中文描述： | 1M X 1 FAST PAGE DRAM, 70 ns, PDSO20 |
| 文件頁數(shù)： | 10/22頁 |
| 文件大小： | 192K |
| 代理商： | HYB511000BJL-70 |
Semiconductor Group
42
HYB 511000BJ/BJL-50/-60/-70
1 M
×
1-DRAM
Notes :
1) All voltages are referenced to
V
SS
.
2)
I
CC1
,
I
CC3
,
I
CC4
,
I
CC6
,
I
CC7
depend on cycle rate.
3)
I
CC1
and
I
CC4
depend on output loading. Specified values are measured with the output open.
4) An initial pause of 200
μ
s is required after power-up followed by 8 RAS cycles before proper device operation
is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles
instead of 8 RAS cycles are required.
5)
V
(min.) and
V
(max.) are reference levels for measuring timing of input signals. Transition times are also
measured between
V
IH
and
V
IL
.
6) Measured with a load equivalent to 2 TTL loads and 100 pF.
7)
t
(max.) defines the time at which the output achieves the open-circuit conditions and is not referenced to
output voltage levels.
8) Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
9) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
10)
t
,
t
,
t
and
t
are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only.
If
t
≥
t
(min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance)
through the entire cycle; if
t
≥
t
(min.),
t
≥
t
(min.) and
t
≥
t
(min.), the cycle is a read-write
cycle and DO will contain data read from the selected cell. If neither of the above sets of conditions is satisfied,
the condition of DO (at access time) is indeterminate.
11) Operation within the
t
(max.) limit insures that
t
RAC
(max.) can be met.
t
RCD
(max.) is specified as a reference
point only. If
t
RCD
is greater than the specified
t
RCD
t
CAC
.
12) Operation within the
t
RAD
(max.) limit insures that
t
RAC
(max.) can be met.
t
RAD
(max.) is specified as a reference
point only. If
t
RAD
is greater than the specified
t
RAD
(max.) limit, then access time is controlled by
t
AA
.
13) AC measurements assume
t
T
= 5ns.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB5116400BJ-50 | 4M x 4-Bit Dynamic RAM |
| HYB5116400BJ-50- | 4M x 4-Bit Dynamic RAM |
| HYB5116400BJ-50-60 | Circular Connector; Body Material:Aluminum; Series:PT06; No. of Contacts:41; Connector Shell Size:22; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Circular Contact Gender:Pin; Insert Arrangement:22-41 |
| HYB5116400BJ-60 | 4M x 4-Bit Dynamic RAM |
| HYB5116400BJ-70 | 4M x 4-Bit Dynamic RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB511000BL-60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM |
| HYB511000BL-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM |
| HYB511000BZ-60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM |
| HYB511000BZ-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM |
| HYB511000BZ-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM |
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