參數(shù)資料
型號(hào)： HYB25D512400AT
廠商： INFINEON TECHNOLOGIES AG
英文描述： CAP .0027UF 16V PPS FILM 0603 2%
中文描述： 512MB的雙倍數(shù)據(jù)速率SDRAM
文件頁(yè)數(shù)： 67/90頁(yè)
文件大?。?/td> 3191K
代理商： HYB25D512400AT
Data Sheet
67
Rev. 1.2, 2004-06
HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Normal Strength Pull-down and Pull-up Characteristics
5.2
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating
Conditions,
I
DD
Specifications and Conditions, and Electrical Characteristics and AC Timing.)
Note:
1. All voltages referenced to
V
SS
.
2. Tests for AC timing,
I
DD
, and electrical, AC and DC characteristics, may be conducted at nominal reference/
supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage
range specified.
3.
Figure 38
represents the timing reference load used in defining the relevant timing parameters of the part. It
is not intended to be either a precise representation of the typical system environment nor a depiction of the
actual load presented by a production tester. System designers will use IBIS or other simulation tools to
correlate the timing reference load to a system environment. Manufacturers will correlate to their production
test conditions (generally a coaxial transmission line terminated at the tester electronics).
4. AC timing and
I
DD
tests may use a
V
IL
to
V
IH
swing of up to 1.5 V in the test environment, but input timing is
still referenced to
V
REF
(or to the crossing point for CK, CK), and parameter specifications are guaranteed for
the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/
ns in the range between
V
IL(AC)
and
V
IH(AC)
.
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively
switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal
does not ring back above (below) the DC input LOW (HIGH) level).
6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating, DDR
SDRAM Slew Rate Standards, Overshoot & Undershoot specification and Clamp
V
-
I
characteristics see the
latest JEDEC specification for DDR components.
Figure 38
AC Output Load Circuit Diagram / Timing Reference Load
AC Timing - Absolute Specifications for PC3200, PC2700 and PC2100
Parameter
Symbol –5
–6
DDR333
Min.
–0.7
–7
DDR266A
Min.
–0.75
Unit
Note/ Test
Condition
1)
DDR400B
Min.
–0.5
Max.
+0.5
Max.
+0.7
Max.
+0.75
DQ output access time from CK/
CK
DQS output access time from CK/
CK
CK high-level width
CK low-level width
t
AC
ns
2)3)4)5)
t
DQSCK
–0.5
+0.5
–0.6
+0.6
–0.75
+0.75
ns
2)3)4)5)
t
CH
t
CL
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
t
CK
t
CK
2)3)4)5)
2)3)4)5)
50
Timing Reference Point
Output
(
V
OUT
)
30 pF
V
TT
相關(guān)PDF資料
PDF描述
HYB25D512400AT-6 512Mbit Double Data Rate SDRAM
HYB25D512400AT-7 512Mbit Double Data Rate SDRAM
HYB25D512800BE-5 512Mbit Double Data Rate SDRAM
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HYB25D512400BE-6 512Mbit Double Data Rate SDRAM
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