參數(shù)資料
型號(hào)： HYB25D512160AT-6
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512Mbit Double Data Rate SDRAM
中文描述： 512MB的雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù)： 23/90頁
文件大?。?/td> 3191K
代理商： HYB25D512160AT-6
Data Sheet
23
Rev. 1.2, 2004-06
HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Functional Description
3.2
Mode Register Definition
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes
the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is
programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored information
until it is programmed again or the device loses power (except for bit A8, which is self-clearing).
Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-
A6 specify the CAS latency, and A7-A12 specify the operating mode.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these requirements results in unspecified operation.
3.2.1
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The
burst length determines the maximum number of column locations that can be accessed for a given Read or Write
command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is
Burst Length
MR
Mode Register Definition
(BA[1:0] = 00
B
)
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
MODE
CL
BT
BL
reg. addr
w
w
w
w
Field
BL
Bits
[2:0]
Type
w
Description
Burst Length
Number of sequential bits per DQ related to one read/write command; see
Chapter 3.2.1
.
Note:All other bit combinations are RESERVED.
001 2
010 4
011 8
Burst Type
See
Table 7
for internal address sequence of low order address bits; see
Chapter 3.2.2
.
0
Sequential
1
Interleaved
CAS Latency
Number of full clocks from read command to first data valid window; see
Chapter 3.2.3
.
Note:All other bit combinations are RESERVED.
BT
3
w
CL
[6:4]
w
010 2
011 3
101 (1.5 Optional, not covered by this data sheet)
110 2.5
Operating Mode
See
Chapter 3.2.4
.
Note:All other bit combinations are RESERVED.
MODE
[12:7] w
000000
000010
Normal Operation without DLL Reset
DLL Reset
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