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參數(shù)資料
| 型號： | HYB25D512160AT-6 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 512Mbit Double Data Rate SDRAM |
| 中文描述： | 512MB的雙倍數(shù)據(jù)速率SDRAM |
| 文件頁數(shù)： | 10/90頁 |
| 文件大?。?/td> | 3191K |
| 代理商： | HYB25D512160AT-6 |
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HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Overview
Data Sheet
10
Rev. 1.2, 2004-06
1.2
Description
The 512Mbit Double Data Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing
536,870,912 bits. It is internally configured as a quad-bank DRAM.
The 512Mbit Double Data Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation.
The double data rate architecture is essentially a
2n
pre fetch architecture with an interface designed to transfer
two data words per clock cycle at the I/O pins. A single read or write access for the 512Mbit Double Data Rate
SDRAM effectively consists of a single
2n
-bit wide, one clock cycle data transfer at the internal DRAM core and
two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver.
DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS
is edge-aligned with data for Reads and center-aligned with data for Writes.
The 512Mbit Double Data Rate SDRAM operates from a differential clock (CK and CK; the crossing of CK going
HIGH and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are
registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an Active command, which is then followed by a Read or Write command. The address bits registered
coincident with the Active command are used to select the bank and row to be accessed. The address bits
registered coincident with the Read or Write command are used to select the bank and the starting column location
for the burst access.
The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto
Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
Note:The functionality described and the timing specifications included in this data sheet are for the DLL Enabled
mode of operation.
Table 2
Part Number
1)
Ordering Information
Org. CAS-RCD-RP
Latencies
×
8
3.0-3-3
×
16
×
4
2.5-3-3
×
8
×
16
×
4
×
4
3.0-3-3
×
8
×
16
×
4
2.5-3-3
×
8
×
16
Clock
(MHz)
200
CAS-RCD-RP
Latencies
2.5-3-3
Clock
(MHz)
133
Speed
Package
HYB25D512800BT–5
HYB25D512160BT–5
HYB25D512400BT–6
HYB25D512800BT–6
HYB25D512160BT–6
HYB25D512400BT–7
HYB25D512400BC–5
HYB25D512800BC–5
HYB25D512160BC–5
HYB25D512400BC–6
HYB25D512800BC–6
HYB25D512160BC–6
DDR400B
P-TSOPII-66
166
2-3-3
133
DDR333
142
200
2.5-3-3
133
DDR400B
P-TFBGA-60
166
2-3-3
133
DDR333
相關(guān)PDF資料 |
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| HYB25D512160AT-7 | 512Mbit Double Data Rate SDRAM |
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| HYB25D512400AT | CAP .0027UF 16V PPS FILM 0603 2% |
| HYB25D512400AT-6 | 512Mbit Double Data Rate SDRAM |
| HYB25D512400AT-7 | 512Mbit Double Data Rate SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D512400BR-7 | 制造商:Infineon Technologies AG 功能描述:128M X 4 DDR DRAM MODULE, P66 Pin Plastic SMT |
| HYB25D512400CE-5 | 制造商:Infineon Technologies AG 功能描述: |
| HYB25D512800CE-5 | 功能描述:IC DDR SDRAM 512MBIT 66TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
| HYB25D512800CE-6 | 功能描述:IC DDR SDRAM 512MBIT 66TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
| HYB25DC512160CE-5 | 制造商:Infineon Technologies AG 功能描述: 制造商:QIMONDA 功能描述: |
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