參數(shù)資料
型號(hào)： HYB25D256800AT-7
英文描述： ?256Mbit (32Mx8) DDR266A (2-3-3)?
中文描述： ？的256Mbit（32Mx8）DDR266A（2-3-3）？
文件頁(yè)數(shù)： 8/76頁(yè)
文件大?。?/td> 1218K
代理商： HYB25D256800AT-7
HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
Page 8 of 76
2002-05-06
Functional Description
The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728
bits. The 128Mb DDR SDRAM is internally configured as a quad-bank DRAM.
The 128Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-
data-rate architecture is essentially a
2n
prefetch architecture, with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the 128Mb DDR SDRAM consists of a
single
2n
-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide,
one-half clock cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the regis-
tration of an Active command, which is then followed by a Read or
W
rite command. The address bits regis-
tered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A11 select the row). The address bits registered coincident with the Read or
W
rite com-
mand are used to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed infor-
mation covering device initialization, register definition, command descriptions and device operation.
Initialization
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other
than those specified may result in undefined operation. The following criteria must be met:
N
o power sequencing is specified during power up or power down given the following criteria:
V
DD
and V
DDQ
are driven from a single power converter output
V
TT
meets the specification
A minimum resistance of 42 ohms limits the input current from the V
TT
supply into any pin and V
REF
tracks V
DDQ
/2
or
The following relationship must be followed:
V
DDQ
is driven after or with V
DD
such that V
DDQ
< V
DD
+ 0.3 V
V
TT
is driven after or with V
DDQ
such that V
TT
< V
DDQ
+ 0.3V
V
REF
is driven after or with V
DDQ
such that V
REF
< V
DDQ
+ 0.3V
The DQ and DQS outputs are in the
H
igh-
Z
state, where they remain until driven in normal operation (by a
read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR
SDRAM requires a 200
μ
s delay prior to applying an executable command.
Once the 200
μ
s delay has been satisfied, a Deselect or
N
OP command should be applied, and CK
E
should
be brought
H
I
GH
. Following the
N
OP command, a Precharge ALL command should be applied.
N
ext a Mode
Register Set command should be issued for the
E
xtended Mode Register, to enable the DLL, then a Mode
Register Set command should be issued for the Mode Register, to reset the DLL, and to program the operat-
ing parameters. 200 clock cycles are required between the DLL reset and any executable command. During
the 200 cycles of clock for DLL locking, a Deselect or
N
OP command must be applied. After the 200 clock
cycles, a Precharge ALL command should be applied, placing the device in the “all banks idle” state.
Once in the idle state, two AUTO R
E
FR
E
S
H
cycles must be performed. Additionally, a Mode Register Set
command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters
without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal
operation.
相關(guān)PDF資料
PDF描述
HYB25D256800AT-7.5 DDR Synchronous DRAM
HYB25D256800AT-8 DDR Synchronous DRAM
HYB25D256800BC-7 ?256Mb (64Mx4) FBGA DDR266A (2-3-3)?
HYB25D256800BT-5 ?256Mbit (32Mx8) DDR400?
HYB25D256800BT-6 ?256Mbit (32Mx8) DDR333 (2.5-3-3)?
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB25D256800AT-7.5 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM
HYB25D256800AT-8 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM
HYB25D256800BC-6 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B
HYB25D256800BC-7 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256Mb (64Mx4) FBGA DDR266A (2-3-3)?
HYB25D256800BC-7F 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM
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