- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367357 > HYB25D256400BT-6 ?256Mbit (64Mx4) DDR333 (2.5-3-3)? PDF資料下載
參數(shù)資料
| 型號： | HYB25D256400BT-6 |
| 英文描述： | ?256Mbit (64Mx4) DDR333 (2.5-3-3)? |
| 中文描述： | ？的256Mbit（64Mx4）DDR333內(nèi)存（2.5-3-3）？ |
| 文件頁數(shù)： | 25/76頁 |
| 文件大?。?/td> | 1218K |
| 代理商： | HYB25D256400BT-6 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
2002-05-06
Page 25 of 76
HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
Data from any Read burst may be truncated with a Burst Terminate command, as shown on
Terminating a
Read Burst: CAS Latencies (Burst Length = 8)
on page 26. The Burst Terminate latency is equal to the read
(CAS) latency, i.e. the Burst Terminate command should be issued x cycles after the Read command, where
x equals the number of desired data element pairs.
Data from any Read burst must be completed or truncated before a subsequent
W
rite command can be
issued. If truncation is necessary, the Burst Terminate command must be used, as shown on
Read to Write:
CAS Latencies (Burst Length = 4 or 8)
on page 27. The example is shown for t
DQSS
(min). The t
DQSS
(max)
case, not shown here, has a longer bus idle time. t
DQSS
(min) and t
DQSS
(max) are defined in the section on
W
rites.
A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that
Auto Precharge was not activated). The Precharge command should be issued x cycles after the Read com-
mand, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch archi-
tecture). This is shown on
Read to Precharge: CAS Latencies (Burst Length = 4 or 8)
on page 28 for Read
latencies of 2 and 2.5. Following the Precharge command, a subsequent command to the same bank cannot
be issued until t
RP
is met.
N
ote that part of the row precharge time is hidden during the access of the last data
elements.
In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as
described above) provides the same operation that would result from the same Read burst with Auto Pre-
charge enabled. The disadvantage of the Precharge command is that it requires that the command and
address busses be available at the appropriate time to issue the command. The advantage of the Precharge
command is that it can be used to truncate bursts.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25D256400BT-7 | ?256Mbit (64Mx4) DDR266A (2-3-3)? |
| HYB25D256400BT-8 | ?256Mbit (64Mx4) DDR200 (2-2-2)? |
| HYB25D256400T-7 | DDR Synchronous DRAM |
| HYB25D256400T-7.5 | DDR Synchronous DRAM |
| HYB25D256400T-8 | DDR Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D256400BT-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256Mbit (64Mx4) DDR266A (2-3-3)? |
| HYB25D256400BT-7F | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM |
| HYB25D256400BT-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256Mbit (64Mx4) DDR200 (2-2-2)? |
| HYB25D256400BTL-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B |
| HYB25D256400BTL-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。