- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367357 > HYB25D256400BC-7 ?256Mb (64Mx4) FBGA DDR266A (2-3-3)? PDF資料下載
參數(shù)資料
| 型號： | HYB25D256400BC-7 |
| 英文描述： | ?256Mb (64Mx4) FBGA DDR266A (2-3-3)? |
| 中文描述： | ？256Mb的（64Mx4）FBGA封裝DDR266A（2-3-3）？ |
| 文件頁數(shù)： | 75/76頁 |
| 文件大?。?/td> | 1218K |
| 代理商： | HYB25D256400BC-7 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁當(dāng)前第75頁第76頁
2002-05-06
Page 75 of 76
HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
TABLE OF CONTENT
Features
1
Description
Pin Configuration
Input/Output Functional Description
Block Diagram (32Mb x 4)
Block Diagram (16Mb x 8)
Block Diagram (8Mb x 16)
1
2
3
5
6
7
Functional Description
Initialization
Register Definition
Mode Register Operation
Burst Definition
Required CAS Latencies
E
xtended Mode Register
E
xtended Mode Register Definition
8
8
9
10
11
12
13
14
Commands
Delesect,
N
o Operation
Mode Register Set
Active
Read
W
rite
Precharge
Auto Precharge
Burst Terminate
Auto Refresh
Self Refresh
15
15
15
15
15
15
15
16
16
16
16
Truth Table 1a: Commands
Truth Table 1b: DM Operation
17
17
Operations
Activating a Specific Row in a Specific Bank
tRCD and tRRD Definition
Read Command
Read Burst
Consecutive Read Bursts
N
on-Consecutive Read Bursts
Random Read Accesses
Terminating a Read Burst
Read to
W
rite
Read to Precharge
W
rite Command
W
rite Burst (Burst Length = 4)
W
rite to
W
rite (Burst Length = 4)
W
rite to
W
rite
Random
W
rite Cycles
18
18
1
9
20
21
22
23
24
26
27
28
30
31
32
33
34
W
rite to Read
W
rite to Read Interrupting
W
rite to Read: Minimum DQSS
W
rite to Read:
N
ominal DQSS
W
rite to Precharge
N
on-Interrupting
W
rite to Precharge Interrupting
W
rite to Precharge Minimum DQSS
W
rite to Precharge:
N
ominal DQSS
Precharge
Power-Down
Truth Table 2: Clock
E
nable (CK
E
)
Truth Table 3: Current State, SameBank
Truth Table 4: Current State,Different Bank
Truth Table 5: Concurrent Auto Precharge
Simplified State Diagram
35
36
37
38
3
9
40
41
42
43
44
45
46
47
48
4
9
Operating Conditions
Absolute Maximum Ratings
Input and Output Capacitances
DC
E
lectrical Operating Conditions
N
ormal Mode Pulldown Characteristics
N
ormal ModePullup Characteristics
N
ormal ModePulldown and Pullup Currents
W
eak Mode Pulldown Characteristics
W
eak ModePullup Characteristics
W
eak ModePulldown and Pullup Currents
IDD Specifications and Conditions
AC Characteristics
AC Output Load Circuit Diagram
AC Operating Conditions
50
50
50
51
52
52
53
54
55
56
56
58
58
60
E
lectrical Characteristics
&
AC Timing
61
Timing Diagrams
Data Input (
W
rite)
Data Output (Read)
Initialize and Mode Register Sets
Power Down Mode
Auto Refresh Mode
Self Refresh Mode
Read without Auto Precharge
Read with Auto Precharge
Bank Read Access
W
rite without Auto Precharge.
W
rite with Auto Precharge
Bank
W
rite Access
W
rite DM Operation
62
62
62
63
64
65
66
67
68
6
9
70
71
72
73
Package Dimensions
Table of Content
Security Information
74
75
76
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25D256400BT-6 | ?256Mbit (64Mx4) DDR333 (2.5-3-3)? |
| HYB25D256400BT-7 | ?256Mbit (64Mx4) DDR266A (2-3-3)? |
| HYB25D256400BT-8 | ?256Mbit (64Mx4) DDR200 (2-2-2)? |
| HYB25D256400T-7 | DDR Synchronous DRAM |
| HYB25D256400T-7.5 | DDR Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D256400BC-7F | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B |
| HYB25D256400BC-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM |
| HYB25D256400BCL-5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM |
| HYB25D256400BCL-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B |
| HYB25D256400BCL-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。