參數(shù)資料
型號(hào)： HYB25D256400BC-7
英文描述： ?256Mb (64Mx4) FBGA DDR266A (2-3-3)?
中文描述： ？256Mb的（64Mx4）FBGA封裝DDR266A（2-3-3）？
文件頁(yè)數(shù)： 29/76頁(yè)
文件大小： 1218K
代理商： HYB25D256400BC-7
2002-05-06
Page 2
9
of 76
HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
Writes
W
rite bursts are initiated with a
W
rite command, as shown on
Write Command
on page 30.
The starting column and bank addresses are provided with the
W
rite command, and Auto Precharge is either
enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at
the completion of the burst. For the generic
W
rite commands used in the following illustrations, Auto Pre-
charge is disabled.
During
W
rite bursts, the first valid data-in element is registered on the first rising edge of DQS following the
write command, and subsequent data elements are registered on successive edges of DQS. The Low state
on DQS between the
W
rite command and the first rising edge is known as the write preamble; the Low state
on DQS following the last data-in element is known as the write postamble. The time between the
W
rite com-
mand and the first corresponding rising edge of DQS (t
DQSS
) is specified with a relatively wide range (from
75
%
to 125
%
of one clock cycle), so most of the
W
rite diagrams that follow are drawn for the two extreme
cases (i.e. t
DQSS
(min) and t
DQSS
(max)).
Write Burst (Burst Length = 4)
on page 31 shows the two extremes of
t
DQSS
for a burst of four. Upon completion of a burst, assuming no other commands have been initiated, the
DQs enters
H
igh-
Z
and any additional input data is ignored.
Data for any
W
rite burst may be concatenated with or truncated with a subsequent
W
rite command. In either
case, a continuous flow of input data can be maintained. The new
W
rite command can be issued on any pos-
itive edge of clock following the previous
W
rite command. The first data element from the new burst is applied
after either the last element of a completed burst or the last desired data element of a longer burst which is
being truncated. The new
W
rite command should be issued x cycles after the first
W
rite command, where x
equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture).
Write to
Write (Burst Length = 4)
on page 32 shows concatenated bursts of 4. An example of non-consecutive
W
rites
is shown on
Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4)
on page 33. Full-speed random
write accesses within a page or pages can be performed as shown on
Random Write Cycles (Burst Length =
2, 4 or 8)
on page 34. Data for any
W
rite burst may be followed by a subsequent Read command. To follow a
W
rite without truncating the write burst, t
W
TR
(
W
rite to Read) should be met as shown on
Write to Read: Non-
Interrupting (CAS Latency = 2; Burst Length = 4)
on page 35.
Data for any
W
rite burst may be truncated by a subsequent Read command, as shown in the figures on
Write
to Read: Interrupting (CAS Latency = 2; Burst Length = 8)
on page 36 to
Write to Read: Nominal DQSS, Inter-
rupting (CAS Latency = 2; Burst Length = 8)
on page 38.
N
ote that only the data-in pairs that are registered
prior to the t
W
TR
period are written to the internal array, and any subsequent data-in must be masked with
DM, as shown in the diagrams noted previously.
Data for any
W
rite burst may be followed by a subsequent Precharge command. To follow a
W
rite without
truncating the write burst, t
W
R
should be met as shown on
Write to Precharge: Non-Interrupting (Burst Length
= 4)
on page 3
9
.
Data for any
W
rite burst may be truncated by a subsequent Precharge command, as shown in the figures on
Write to Precharge: Interrupting (Burst Length = 4 or 8)
on page 40 to
Write to Precharge: Nominal DQSS (2
bit Write), Interrupting (Burst Length = 4 or 8)
on page 42.
N
ote that only the data-in pairs that are registered
prior to the t
W
R
period are written to the internal array, and any subsequent data in should be masked with
DM. Following the Precharge command, a subsequent command to the same bank cannot be issued until t
RP
is met.
In the case of a
W
rite burst being executed to completion, a Precharge command issued at the optimum time
(as described above) provides the same operation that would result from the same burst with Auto Pre-
charge. The disadvantage of the Precharge command is that it requires that the command and address bus-
ses be available at the appropriate time to issue the command. The advantage of the Precharge command is
that it can be used to truncate bursts.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB25D256400BC-7F 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B
HYB25D256400BC-8 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM
HYB25D256400BCL-5 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM
HYB25D256400BCL-6 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B
HYB25D256400BCL-7 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM
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