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參數(shù)資料
| 型號： | HYB18RL25616AC-4 |
| 英文描述： | ?256M (16Mx16) 250MHz ? |
| 中文描述： | ？256M（16Mx16顯示）250MHz的？ |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 869K |
| 代理商： | HYB18RL25616AC-4 |
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HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Version 1.42
Page 16
Infineon Technologies
This specification is preliminary and subject to change without notice
2.3
Mode Register Set Command (MRS)
The mode register stores the data for controlling the operating modes of
the memory. It programs the RLDRAM configuration, burst length, test
mode and IO options. During a Mode Register Set command the address
inputs A<17:0> are sampled and stored in the mode register. tMRSC
must be met before any command can be issued to the RLDRAM. The
mode register may only be set immediately after power up sequence.
Figure 9
Mode Register Set Timing
Table 7
Timing Parameters MRS
Figure 10 Mode Register Bitmap
Note: 1 HSTL compliant current specification
Note: 2 Bits A<17:6> must be set to zero
Note: 3 Automatic IO impedance calibration is activated in Matched Mode
Parameter
Symbol
-3.3
-4.0
-5.0
Units
Notes
min
max
min
max
min
max
Mode Register Set cycle time
t
MRSC
4
–
4
–
4
–
tCK
CK#
CK
WE#
REF#
A[17:0]
Don't Care
COD: Code to be loaded into
the register
CS#
COD
A[19:18]
BA<2:0>
AS#
Figure 8
Mode Register Set
CK#
CK
Don't Care
t
MRSC
Command
MRS:
command
A.C.:
MRS
Any command
MRS
NOP
A.C.
NOP
RLDRAM Configuration
A3
0
1
Burst Length
2 (default)
4
RLDRAM
configuration
A2
A1
A0
Do not use
1
1
0
4
1
0
0
Do not use
1
0
1
A2
A4
A5
A6
A<17:7>
A3
3
0
1
1
1
0
0
1
2
0
1
0
3 (default)
0
0
0
Burst
Length
Matched
Mode
Driver
Strength
Test Mode
Reserved
2
A1
A0
A4
0
1
Matched Mode
inactive (default)
active
3
A5
0
1
Driver Strength
1
8mA (default)
Do not use
A6
0
1
Test Mode
(default)
test mode
1
1
1
Do not use
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