參數(shù)資料
型號(hào)： HYB18L256160BF-75
廠商： INFINEON TECHNOLOGIES AG
英文描述： DRAMs for Mobile Applications
中文描述： 針對(duì)移動(dòng)應(yīng)用的DRAM
文件頁(yè)數(shù)： 45/49頁(yè)
文件大?。?/td> 1327K
代理商： HYB18L256160BF-75
HY[B/E]18L256160B[C/F]-7.5
256-Mbit Mobile-RAM
Electrical Characteristics
Data Sheet
45
V1.4, 2004-04-30
3.2
AC Characteristics
Table 20
Parameter
AC Characteristics
1)2)3)4)
1) 0
°
C
≤
T
C
≤
70
°
C (comm.); -25
°
C
≤
T
C
≤
85
°
C (ext.);
V
DD
=
V
DDQ
= 1.8 V
±
0.15 V;
2) All parameters assumes proper device initialization.
3) AC timing tests measured at 0.9 V.
4) The transition time
t
T
is measured between
V
IH
and
V
IL
; all AC characteristics assume
t
T
= 1 ns.
5) Specified
t
AC
and
t
OH
parameters are measured with a 30 pF capacitive load only as shown below:
Symbol
- 7.5
Unit
Notes
min.
7.5
9.5
–
–
–
–
2.5
2.5
1.5
0.8
2
1.0
3.0
2.5
–
0
67
19
15
45
14
19
–
1
max.
–
–
133
105
5.4
6.0
–
–
–
–
–
–
7.0
–
2
–
–
–
–
100k
–
–
64
–
Clock cycle time
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
t
CK
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
t
CK
ns
ns
ns
t
CK
t
CK
ns
ns
ns
ns
ns
ns
ms
t
CK
–
Clock frequency
f
CK
–
Access time from CLK
t
AC
5)6)
6) If
t
T
(CLK) > 1 ns, a value of (
t
T
/2 - 0.5) ns has to be added to this parameter.
7) If
t
T
> 1 ns, a value of (
t
T
- 1) ns has to be added to this parameter.
8) These parameter account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
9) The write recovery time of
t
WR
= 14 ns allows the use of one clock cycle for the write recovery time when
f
CK
≤
72 MHz.
With
f
CK
> 72 MHz two clock cycles for
t
WR
are mandatory. Infineon Technologies recommends to use two clock cycles for
the write recovery time in all applications.
Clock high-level width
Clock low-level width
Address, data and command input setup time
Address, data and command input hold time
MODE REGISTER SET command period
DQ low-impedance time from CLK
DQ high-impedance time from CLK
Data out hold time
DQM to DQ High-Z delay (READ Commands)
DQM write mask latency
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE bank A to ACTIVE bank B delay
ACTIVE to PRECHARGE command period
WRITE recovery time
PRECHARGE command period
Refresh period (8192 rows)
Self refresh exit time
t
CH
t
CL
t
IS
t
IH
t
MRD
t
LZ
t
HZ
t
OH
t
DQZ
t
DQW
t
RC
t
RCD
t
RRD
t
RAS
t
WR
t
RP
t
REF
t
SREX
–
–
7)
7)
–
–
–
5)6)
–
–
8)
8)
8)
8)
9)
8)
–
–
30 pF
I/O
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