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參數(shù)資料
| 型號： | HYB 25M144180C |
| 廠商： | SIEMENS AG |
| 英文描述： | 144-MBit Direct RDRAM(144 M位直接RDRAM) |
| 中文描述： | 144兆位的直接的RDRAM（144米位直接的RDRAM） |
| 文件頁數(shù)： | 10/93頁 |
| 文件大?。?/td> | 919K |
| 代理商： | HYB 25M144180C |
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Direct RDRAM
128/144-MBit (256K
×
16/18
×
32s)
Data Book
10
2.00
Field Encoding Summary
Table 7
shows how the six device address bits are decoded for the ROWA and ROWR packets.
The DR4T and DR4F encoding merges a fifth device bit with a framing bit. When neither bit is
asserted, the device is not selected. Note that a broadcast operation is indicated when both bits are
set. Broadcast operation would typically be used for refresh and power management commands. If
the device is selected, the DM (DeviceMatch) signal is asserted and an ACT or ROP command is
performed.
Table 8
shows the encodings of the remaining fields of the ROWA and ROWR packets. An ROWA
packet is specified by asserting the AV bit. This causes the specified row of the specified bank of this
device to be loaded into the associated sense amps.
An ROWR packet is specified when AV is not asserted. An 11 bit opcode field encodes a command
for one of the banks of this device. The PRER command causes a bank and its two associated
sense amps to precharge, so another row or an adjacent bank may be activated. The REFA
(refresh-activate) command is similar to the ACT command, except the row address comes from an
internal register REFR, and REFR is incremented at the largest bank address. The REFP (refresh-
precharge) command is identical to a PRER command.
The NAPR, NAPRC, PDNR, ATTN, and RLXR commands are used for managing the power
dissipation of the RDRAM and are described in more detail in “Power State Management” on
page 58. The TCEN and TCAL commands are used to adjust the output driver slew rate and they
are described in more detail in “Current and Temperature Control” on page 65.
Table 7
Device Field Encodings for ROWA Packet and ROWR Packet
DR4T DR4F Device Selection
Device Match Signal (DM)
1
1
All devices (broadcast) DM is set to 1
0
1
One device selected
DM is set to 1 if {DEVID4 … DEVID0} == {0, DR3 … DR0}
else DM is set to 0
1
0
One device selected
DM is set to 1 if {DEVID4 … DEVID0} == {1, DR3 … DR0}
else DM is set to 0
0
0
No packet present
DM is set to 0
相關PDF資料 |
PDF描述 |
|---|---|
| HYB25R144180C | 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) |
| HYB3116160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3118160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-60 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3118160BST-60 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BST-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
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