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參數(shù)資料
| 型號(hào)： | HY62UF16201A |
| 廠(chǎng)商： | Hynix Semiconductor Inc. |
| 英文描述： | 128Kx16bit full CMOS SRAM |
| 中文描述： | 128Kx16bit充分的CMOS的SRAM |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大?。?/td> | 254K |
| 代理商： | HY62UF16201A |
HY62UF16201A Series
WRITE CYCLE 1 (1,4,8) (/WE Controlled)
WRITE CYCLE 2 (1,4,8) (/CS Controlled)
Notes:
1. A write occurs during the overlap of a low /WE, a low /CS1 and low /UB and/or /LB.
2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured +200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
Rev.08 / Mar. 2002
6
Data Valid
ADDR
Data
Out
/
CS
/
UB
,
/
LB
/
WE
tWC
tCW
tWR
(2)
tBW
tAW
tWP
Data In
High-Z
tAS
tWHZ
(3,7)
tDW
tDH
tOW
(5)
(6)
Data Valid
ADDR
Data
Out
/
CS
/
UB
,
/
LB
/
WE
tWC
tCW
tWR
(2)
tBW
tAW
tWP
Data In
tDW
tDH
High-Z
High-Z
tAS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY62UF16201A-I | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:128Kx16bit full CMOS SRAM |
| HY62UF16201ALLF10IR | 制造商:HYNIX 功能描述:* |
| HY62UF16403A | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x16|3V|55/70/85|Super Low Power Slow SRAM - 4M |
| HY62UF16403A-I | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:256Kx16bit full CMOS SRAM |
| HY62UF16403ALLM | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:256Kx16bit full CMOS SRAM |
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