參數(shù)資料
型號(hào): HY62UF16201A-I
廠商: Hynix Semiconductor Inc.
英文描述: 128Kx16bit full CMOS SRAM
中文描述: 128Kx16bit充分的CMOS的SRAM
文件頁(yè)數(shù): 6/11頁(yè)
文件大?。?/td> 254K
代理商: HY62UF16201A-I
HY62UF16201A Series
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
READ CYCLE 2(Note 2,3,4)
tRC
Rev.08 / Mar. 2002
5
READ CYCLE 3(Note 1,2,4)
ADDR
Data
Out
tAA
Data Valid
Previous Data
tOH
tOH
Notes:
A read occurs during the overlap of a low /OE, a high /WE, a low /CS1 and low /UB and/or /LB.
2. /OE = V
IL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
/CS
/UB, /LB
Data
Out
tACS
Data Valid
tCLZ(3)
tCHZ(3)
ADDR
tRC
/CS
tAA
tACS
tOH
Data Valid
High-Z
Data
Out
/UB ,/ LB
/OE
tBA
tOE
tCLZ
(3)
tBLZ
(3)
tOLZ
(3)
tCHZ
(3)
tBHZ
(3)
tOHZ
(3)
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