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參數(shù)資料
| 型號： | HY5PS12823LF |
| 英文描述： | 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| 中文描述： | 64Mx8 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II內(nèi)存- 512M |
| 文件頁數(shù)： | 39/66頁 |
| 文件大?。?/td> | 862K |
| 代理商： | HY5PS12823LF |
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Rev. 0.52/Nov. 02 39
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
FUNCTION DESCRIPTION
Bank Active Operation
Bank active should be issued to activate (or open) a row in particular bank for a subsequent read or write access. Bank
active command is issued by holding CS and RAS low, CAS and WE high at the rising edge of clock. Bank address and
row address provided on inputs BA0~BA1 and A0~A13 selects the bank and row. Minumun delay between bank active
to read or write command is determined by additive latency, which programmed to EMRS. When additive latency value
zero is programmed to EMRS, minumun delay between bank active to read or write command is tRCD (RAS to CAS
delay). In that case, operation is the same with normal SDRAM and DDR SDRAM. But,. when the other additive latency
values are programmed to EMRS, read or write command could be issued without time delay of tRCD (RAS to CAS
delay). But, if read or write command are issued earlier than minimum tRCD delay, proper addtive latency value must
be chosen to insure and that value must be programmed to EMRS.
To select different row in the same bank, activated bank must be prechareged prior to bank active. Minimum interval
between successive bank activate commands to the same bank is determined by the tRC (RAS cycle time), which is
equal to tRAS + tRP. To ensure proper operation, minimun delay of tRAS and tRP must be maintained.
/CK
CK
Active
Bank A
Q0 Q1 Q2 Q3
Read
Bank A
tRCD
CAS latency = 3clks
CMD
DQS
DQ
PRE
Bank A
Active
Bank A
tRP
tRAS
tRC
Active
Bank B
Active
Q0 Q1 Q2 Q3
Read
Read latency = 5clks
Additive Latency = 2clks
CMD
DQS
DQ
Q0 Q1 Q2 Q3
Read
tRRD
Read latency = 5clks
tRCD=3CLKs, tRP=3CLKs, CL=3CLKs, AL=0CLK
tRCD=3CLKs, tRRD=2CLKs, CL=3CLKs, AL=2CLKs
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