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參數(shù)資料
| 型號： | HY5PS12823LF |
| 英文描述： | 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| 中文描述： | 64Mx8 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II內(nèi)存- 512M |
| 文件頁數(shù)： | 27/66頁 |
| 文件大?。?/td> | 862K |
| 代理商： | HY5PS12823LF |
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Rev. 0.52/Nov. 02 27
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
EXTENDED MODE REGISTER SET (EMRS)
The extended mode register is used to store the various operating modes such as DLL disabling, output driver
strength, Additive Latency, ODT value selection, OCD programming, DQS and RDQS disabling. The extended mode
register is program via MRS command. This command is issued by the low signals of RAS, CAS, CS , WE and high sig-
nals of BA0. This command can be issued only when all banks are in idle state and CKE must be high at least one cycle
before the Mode Register Set Command can be issued. The mode register set command time(tMRD) must be satisfied
to write the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field
is determined, the information will be held until resetted by another EMRS command.
BA1
BA0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
0
0
RDQS /DQS
OCD Program
RTT
Additive Latency
RTT
DIC
DLL
A0
DLL Enable
0
Enable
1
Disable
BA0
MRS Type
0
MRS
1
EMRS(1)
A1
Output Driver
Impedance Control
0
Full Strength Driver
1
Half Strength Driver
* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage.
A5
A4
A3
Additive
Latency
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
Reserved
1
1
1
Reserved
A6
A2
RTT(nominal)
0
0
ODT Disable
0
1
75ohm
1
0
150ohm
1
1
Reserved
Off-Chip-Driver program
A9
A8
A7
Operation
0
0
0
OCD calibration mode exit
0
0
1
Drive(1)
0
1
0
Drive(0)
0
1
1
Adjust mode
1
1
1
OCD calibration default
A10
DQS Enable
0
Enable
1
Disable
A11
RDQS Enable
0
Disable
1
Enable
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