- 您現(xiàn)在的位置：買賣IC網 > PDF目錄385428 > HY5DV281622DT-4 (HYNIX SEMICONDUCTOR INC) 128M(8Mx16) GDDR SDRAM PDF資料下載
參數資料
| 型號： | HY5DV281622DT-4 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 128M(8Mx16) GDDR SDRAM |
| 中文描述： | 8M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件頁數： | 19/31頁 |
| 文件大?。?/td> | 294K |
| 代理商： | HY5DV281622DT-4 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
Rev. 0.5 / Aug. 2003
19
HY5DV281622DT
BURST DEFINITION
BURST LENGTH & TYPE
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst
length determines the maximum number of column locations that can be accessed for a given Read or Write com-
mand. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is
set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a
given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to both Read and Write bursts.
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Burst Definitionon Table
Burst Length
Starting Address (A2,A1,A0)
Sequential
Interleave
2
XX0
0, 1
0, 1
XX1
1, 0
1, 0
4
X00
0, 1, 2, 3
0, 1, 2, 3
X01
1, 2, 3, 0
1, 0, 3, 2
X10
2, 3, 0, 1
2, 3, 0, 1
X11
3, 0, 1, 2
3, 2, 1, 0
8
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
相關PDF資料 |
PDF描述 |
|---|---|
| HY5DV281622DT-5 | 128M(8Mx16) GDDR SDRAM |
| HY5DV281622DT-6 | 128M(8Mx16) GDDR SDRAM |
| HY5DV641622AT | 64M(4Mx16) DDR SDRAM |
| HY5DV641622AT-33 | 64M(4Mx16) DDR SDRAM |
| HY5DV641622AT-36 | 64M(4Mx16) DDR SDRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HY5DV281622DT-5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM |
| HY5DV281622DT-6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM |
| HY5DV281622DTP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM |
| HY5DV281622DTP-33 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM |
| HY5DV281622DTP-36 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。