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參數資料
| 型號： | HY5DU121622CTP-5 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 512Mb(32Mx16) GDDR SDRAM |
| 中文描述： | 32M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件頁數： | 27/29頁 |
| 文件大小： | 233K |
| 代理商： | HY5DU121622CTP-5 |
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Rev. 0.3 / Apr. 2005
27
1
HY5DU121622CTP
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to
n-channel variation of the output drivers.
11. This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF
+/-310mV for a duration of up to 2ns.
13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and
DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1 =
0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.
14.
DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal tran-
sitions through the DC region must be monotonic.
15. tDAL = 2 clocks + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer.
tCK is equal to the actual system clock cycle time.
Example: 200MHz at CL=3 and tCK = 5 ns,
tDAL = (15 ns / 5ns) + (15 ns / 5 ns) = (3.0) + (3.0)
Round up each non-integer to the next highest integer: = (3) + (4), tDAL = 6 clocks
16.
For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be tRAS - BL/2 x
tCK.
Input Setup / Hold Slew-rate
Delta tDS
Delta tDH
V/ns
ps
ps
0.5
0
0
0.4
+75
+75
0.3
+150
+150
I/O Input Level
Delta tDS
Delta tDH
mV
ps
ps
+280
+50
+50
(1/SlewRate1)-(1/SlewRate2)
Delta tDS
Delta tDH
ns/V
ps
ps
0
0
0
+/-0.25
+50
+50
+/- 0.5
+100
+100
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| HY5DU121622B | 512Mb DDR SDRAM |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HY5DU121622CTP-6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb(32Mx16) GDDR SDRAM |
| HY5DU121622CTP-X | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
| HY5DU121622DFP-D43 | 制造商:SK Hynix Inc 功能描述: |
| HY5DU121622DFP-D43I | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
| HY5DU121622DFP-H | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
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