參數(shù)資料
型號(hào): HY5DU121622CTP-5
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 512Mb(32Mx16) GDDR SDRAM
中文描述: 32M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝: 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66
文件頁(yè)數(shù): 25/29頁(yè)
文件大?。?/td> 233K
代理商: HY5DU121622CTP-5
Rev. 0.3 / Apr. 2005
25
1
HY5DU121622CTP
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
Parameter
Symbol
4
5
6
Unit
Note
Min
Max
Min
Max
Min
Max
Row Cycle Time
tRC
15
-
12
-
10
-
tCK
Auto Refresh Row Cycle Time
tRFC
15
-
14
-
12
-
tCK
Row Active Time
tRAS
40
100K
40
100K
42
100K
ns
Active to Read with Auto
Precharge Delay
tRAP
tRCD or
tRASmin
-
tRCD or
tRASmin
-
tRCD or
tRASmin
-
ns
16
Row Address to Column
Address Delay
tRCD
5
-
4
-
3
-
tCK
Row Active to Row Active Delay
tRRD
2
-
2
-
2
-
tCK
Column Address to Column
Address Delay
tCCD
1
-
1
-
1
-
tCK
Row Precharge Time
tRP
5
-
4
-
3
-
tCK
Write Recovery Time
tWR
3
-
3
-
3
-
tCK
Internal Write to Read
Command Delay
tWTR
2
-
2
-
2
-
tCK
Auto Precharge Write Recovery
+
Precharge Time
tDAL
8
-
7
-
6
-
tCK
15
System Clock Cycle
Time
CL = 3
tCK
4
7
5
10
6
10
ns
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Data-Out edge to Clock edge
Skew
tAC
-0.7
0.7
-0.7
0.7
-0.7
0.7
ns
DQS-Out edge to Clock edge
Skew
tDQSCK
-0.7
0.7
-0.7
0.7
-0.7
0.7
ns
DQS-Out edge to Data-Out
edge Skew
tDQSQ
-
0.4
-
0.4
-
0.45
ns
Data-Out hold time from DQS
tQH
t
HP
-t
QHS
-
t
HP
-t
QHS
-
t
HP
-t
QHS
-
ns
1,10
Clock Half Period
tHP
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-
ns
1,9
Data Hold Skew Factor
tQHS
-
0.4
-
0.4
-
0.45
ns
10
Input Setup Time
tIS
0.6
-
0.6
-
0.75
-
ns
2,3,
5,6
Input Hold Time
tIH
0.6
-
0.6
-
0.75
-
ns
Write DQS High Level Width
t
DQSH
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write DQS Low Level Width
t
DQSL
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Clock to First Rising
edge of DQS-In
t
DQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
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