參數(shù)資料
型號(hào)： HY5DS573222F-28
廠商： HYNIX SEMICONDUCTOR INC
元件分類(lèi)： DRAM
英文描述： 256M(8Mx32) GDDR SDRAM
中文描述： 8M X 32 DDR DRAM, 0.6 ns, PBGA144
封裝： 12 X 12 MM, 0.80 MM PITCH, MO-205DAE, FBGA-144
文件頁(yè)數(shù)： 25/28頁(yè)
文件大?。?/td> 326K
代理商： HY5DS573222F-28
1
HY5DS573222F(P)
Rev. 1.0 / Feb. 2005
25
N
ote :
1.
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2.
Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3.
Data latched at both rising and falling edges of Data Strobes(DQS0~DQS3) : DQ, DM(0~3).
4.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
5.
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
6. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL).
tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and
output pattern effects, and p-channel to n-channel variation of the output drivers.
7. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transitions through the DC region must be monotonic.
Data-In Setup Time to DQS-In
(DQ & DM)
t
DS
0.35
-
0.35
-
0.4
-
0.4
-
ns
3
Data-In Hold Time to DQS-In
(DQ & DM)
t
DH
0.35
-
0.35
-
0.4
-
0.4
-
ns
3
Read DQS Preamble Time
t
RPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
CK
Read DQS Postamble Time
t
RPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CK
Write DQS Preamble Setup Time
t
WPRES
0
-
0
-
0
-
0
-
ns
Write DQS Preamble Hold Time
t
WPREH
0.35
-
0.35
-
0.35
-
0.35
-
CK
Write DQS Postamble Time
t
WPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CK
Mode Register Set Delay
t
MRD
2
-
2
-
2
-
2
-
CK
Exit Self Refresh to Any Execute
Command
t
XSC
200
-
200
-
200
-
200
-
CK
4
Power Down Exit Time
t
PDEX
2tCK
+ tIS
-
2tCK
+ tIS
-
1tCK
+ tIS
-
1tCK
+ tIS
-
CK
Average Periodic Refresh Interval
t
REFI
-
7.8
-
7.8
-
7.8
-
7.8
us
Parameter
Symbol
28
33
36
4
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
相關(guān)PDF資料
PDF描述
HY5DS573222F-33 256M(8Mx32) GDDR SDRAM
HY5DS573222F-36 256M(8Mx32) GDDR SDRAM
HY5DS573222F-4 256M(8Mx32) GDDR SDRAM
HY5DS573222FP 256M(8Mx32) GDDR SDRAM
HY5DS573222FP-28 256M(8Mx32) GDDR SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HY5DS573222F-33 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:256M(8Mx32) GDDR SDRAM
HY5DS573222F-36 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:256M(8Mx32) GDDR SDRAM
HY5DS573222F-4 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:256M(8Mx32) GDDR SDRAM
HY5DS573222FP 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:256M(8Mx32) GDDR SDRAM
HY5DS573222FP-28 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:256M(8Mx32) GDDR SDRAM
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*