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參數(shù)資料
| 型號： | HY57V641620ESTP-7 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O |
| 中文描述： | 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-54 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大小： | 122K |
| 代理商： | HY57V641620ESTP-7 |
Rev. 1.5 / Feb. 2005
2
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620E(L/S)T(P) Series
DESCRIPTION
The Hynix HY57V641620E(L/S)T(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory
applications which require wide data I/O and high bandwidth. HY57V641620E(L/S)T(P) is organized as 4banks of
1,048,576x16.
HY57V641620E(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs
and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve
very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-
stricted by a '2N' rule)
FEATURES
Voltage: VDD, VDDQ 3.3V supply voltage
ORDERING INFORMATION
Note:
1. HY57V641620ET Series: Normal power, Leaded.
2. HY57V641620ELT Series: Low power, Leaded.
3. HY57V641620EST Series: Super Low power, Leaded.
4. HY57V641620ETP Series: Normal power, Lead Free.
5. HY57V641620ELTP Series: Low power, Lead Free.
6. HY57V641620ESTP Series: Super Low Power, Lead Free
Part No.
Clock Frequency
Organization
Interface
Package
HY57V641620E(L/S)T(P)-5
200MHz
4Banks x 1Mbits x16
LVTTL
54 Pin TSOPII
HY57V641620E(L/S)T(P)-6
166MHz
HY57V641620E(L/S)T(P)-7
143MHz
HY57V641620E(L/S)T(P)-H
133MHz
All device pins are compatible with LVTTL interface
54 Pin TSOPII (Lead or Lead Free Package)
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM, LDQM
Internal four banks operation
Auto refresh and self refresh
4096 Refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency; 2, 3 Clocks
Burst Read Single Write operation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY57V641620ESTP-H | 64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O |
| HY57V641620ET | 64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O |
| HY57V641620ET-5 | 64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O |
| HY57V641620ET-6 | 64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O |
| HY57V641620ET-7 | 64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY57V641620ESTP-H | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O |
| HY57V641620ET | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O |
| HY57V641620ET-5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O |
| HY57V641620ET-6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O |
| HY57V641620ET-7 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O |
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