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參數資料
| 型號： | HY57V281620ALT-HI |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 4 Banks x 2M x 16bits Synchronous DRAM |
| 中文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 |
| 文件頁數： | 7/11頁 |
| 文件大?。?/td> | 81K |
| 代理商： | HY57V281620ALT-HI |
HY57V281620A
Rev. 0.4/Apr.01
7
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter
2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v
If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Parameter
S y m b o l
-KI
- H I
-PI
- S I
Unit
Note
Min
M a x
Min
M a x
Min
M a x
Min
Max
System Clock
Cycle Time
C A S Latency = 3
t C K 3
7.5
1000
7.5
1000
10
1 0 0 0
10
1000
ns
C A S Latency = 2
t C K 2
7.5
10
10
12
ns
Clock High Pulse Width
t C H W
2.5
-
2.5
-
3
-
3
-
ns
1
Clock Low Pulse Width
t C L W
2.5
-
2.5
-
3
-
3
-
ns
1
Access Time
From Clock
C A S Latency = 3
t A C 3
-
5.4
-
5.4
-
6
-
6
ns
2
C A S Latency = 2
t A C 2
-
5.4
-
6
-
6
-
6
ns
Data-Out Hold Time
t O H
2.5
-
2.5
-
2.5
-
2.5
-
ns
Data-Input Setup Time
tDS
1.5
-
1.5
-
2
-
2
-
ns
1
Data-Input Hold Time
tDH
0.8
-
0.8
-
1
-
1
-
ns
1
Address Setup Time
tAS
1.5
-
1.5
-
2
-
2
-
ns
1
Address Hold Time
tAH
0.8
-
0.8
-
1
-
1
-
ns
1
C K E S e t u p T i m e
t C K S
1.5
-
1.5
-
2
-
2
-
ns
1
C K E H o l d T i m e
t C K H
0.8
-
0.8
-
1
-
1
-
ns
1
C o m m a n d S e t u p T i m e
tCS
1.5
-
1.5
-
2
-
2
-
ns
1
Command Hold Time
tCH
0.8
-
0.8
-
1
-
1
-
ns
1
CLK to Data Output in Low-Z Time
tOLZ
1
-
1
-
1
-
1
-
ns
CLK to Data
Output in High-Z
Time
C A S Latency = 3
tOHZ3
2.7
5.4
2.7
5.4
3
6
3
6
ns
C A S Latency = 2
tOHZ2
2.7
5.4
3
6
3
6
3
6
ns
相關PDF資料 |
PDF描述 |
|---|---|
| HY57V281620ALT-KI | 4 Banks x 2M x 16bits Synchronous DRAM |
| HY57V281620ELT-H | 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
| HY57V281620ELT | 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
| HY57V281620ELT-5 | 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
| HY57V281620ELT-6 | 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HY57V281620ALT-I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx16|3.3V|4K|K|SDR SDRAM - 128M |
| HY57V281620ALT-K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HY57V281620ALT-KI | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 2M x 16bits Synchronous DRAM |
| HY57V281620ALT-P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HY57V281620ALT-PI | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 2M x 16bits Synchronous DRAM |
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