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參數(shù)資料
| 型號： | HY57V281620ALT-HI |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 4 Banks x 2M x 16bits Synchronous DRAM |
| 中文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 81K |
| 代理商： | HY57V281620ALT-HI |
HY57V281620A
Rev. 0.4/Apr.01
2
PIN CONFIGURATION
PIN DESCRIPTION
PIN
P I N N A M E
D E S C R I P T I O N
C L K
C l o c k
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
C K E
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
C S
Chip Select
Enables or disables all inputs except CLK, CKE, UDQM and LDQM
B A 0 , B A 1
Bank Address
Selects bank to be activated during R A S activity
Selects bank to be read/written during C A S activity
A 0 ~ A 1 1
Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
R A S , C A S, W E
Row Address Strobe, Col-
umn Address Strobe, Write
Enable
R A S , C A S and W E define the operation
Refer function truth table for details
U D Q M , L D Q M
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
D Q 0 ~ D Q 1 5
Data Input/Output
Multiplexed data input / output pin
V
DD
/V
SS
Power Supply/Ground
Power supply for internal circuits and input buffers
V
D D Q
/V
S S Q
Data Output Power/Ground
Power supply for output buffers
N C
No Connection
No connection
V
SS
D Q 1 5
V
SSQ
D Q 1 4
D Q 1 3
V
DDQ
D Q 1 2
D Q 1 1
V
SSQ
D Q 1 0
D Q 9
V
DDQ
D Q 8
V
SS
N C
U D Q M
C L K
C K E
N C
A11
A 9
A 8
A 7
A 6
A 5
A 4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
DD
D Q 0
V
DDQ
D Q 1
D Q 2
V
SSQ
D Q 3
D Q 4
V
DDQ
D Q 5
D Q 6
V
SSQ
D Q 7
V
DD
L D Q M
/ W E
/CAS
/RAS
/ C S
B A 0
B A 1
A10/AP
A 0
A 1
A 2
A 3
V
DD
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY57V281620ALT-KI | 4 Banks x 2M x 16bits Synchronous DRAM |
| HY57V281620ELT-H | 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
| HY57V281620ELT | 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
| HY57V281620ELT-5 | 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
| HY57V281620ELT-6 | 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY57V281620ALT-I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx16|3.3V|4K|K|SDR SDRAM - 128M |
| HY57V281620ALT-K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HY57V281620ALT-KI | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 2M x 16bits Synchronous DRAM |
| HY57V281620ALT-P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HY57V281620ALT-PI | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 2M x 16bits Synchronous DRAM |
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