參數資料
型號: HW-V5-ML501-UNI-G-J
廠商: Xilinx Inc
文件頁數: 47/91頁
文件大小: 0K
描述: EVALUATION PLATFORM VIRTEX-5
標準包裝: 1
系列: Virtex®-5 LX
類型: FPGA
適用于相關產品: XC5VLX50FFG676
所含物品: ML501 平臺、DVI 適配器和 CompactFlash 卡
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
51
Configuration Switching Characteristics
Table 70: Configuration Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
Power-up Timing Characteristics
TPL
Program Latency
3
ms, Max
TPOR
Power-on-Reset
10
50
10
50
10
50
ms, Min/Max
TICCK
CCLK (output) delay
400
ns, Min
TPROGRAM
Program Pulse Width
250
ns, Min
Master/Slave Serial Mode Programming Switching(1)
TDCCK/TCCKD
DIN Setup/Hold, slave mode
4.0
0.0
4.0
0.0
4.0
0.0
ns, Min
TDSCCK/TSCCKD
DIN Setup/Hold, master mode
4.0
0.0
4.0
0.0
4.0
0.0
ns, Min
TCCO
DOUT
7.5
ns, Max
FMCCK
Maximum Frequency, master mode with
respect to nominal CCLK.
100
MHz,
Max
FMCCKTOL
Frequency Tolerance, master mode with
respect to nominal CCLK.
±50
%
FMSCCK
Slave mode external CCLK
100
MHz
SelectMAP Mode Programming Switching(1)
TSMDCCK/TSMCCKD
SelectMAP Data Setup/Hold
3.0
0.5
3.0
0.5
3.0
0.5
ns, Min
TSMCSCCK/TSMCCKCS
CS_B Setup/Hold
3.0
0.5
3.0
0.5
3.0
0.5
ns, Min
TSMCCKW/TSMWCCK
RDWR_B Setup/Hold
8.0
0.5
8.0
0.5
8.0
0.5
ns, Min
TSMCKCSO
CSO_B clock to out
(330
Ω pull-up resistor required)
10
ns, Min
TSMCO
CCLK to DATA out in readback
9.0
ns, Max
TSMCKBY
CCLK to BUSY out in readback
7.5
ns, Max
FSMCCK
Maximum Frequency with respect to nominal
CCLK.
100
MHz, Max
FRBCCK
Maximum Readback Frequency with respect
to nominal CCLK
60
MHz, Max
FMCCKTOL
Frequency Tolerance with respect to nominal
CCLK.
±50
%
Boundary-Scan Port Timing Specifications
TTAPTCK
TMS and TDI Setup time before TCK
1.0
ns, Min
TTCKTAP
TMS and TDI Hold time after TCK
2.0
ns, Min
TTCKTDO
TCK falling edge to TDO output valid
6
ns, Max
FTCK
Maximum configuration TCK clock frequency
66
MHz, Max
FTCKB
Maximum boundary-scan TCK clock
frequency
66
MHz, Max
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