HT95C200/20P/300/30P
Rev. 0.10
15
October 1, 2002
Preliminary
If the instruction clock is selected as the WDT clock
source, the WDT operates in the same manner except
in the Sleep mode or Idle mode. In these two modes, the
WDT stops counting and lose its protecting purpose. In
this situation the logic can only be re-started by external
logic.
If the WDT clock source is the 32768Hz, the WDT also
operates in the same manner except in the Idle mode.
When in the Idle mode, the 32768Hz stops, the WDT
stops counting and lose its protecting purpose. In this
situation the logic can only be re-started by external
logic.
The high nibble and bit3 of the WDTS are reserved for
user defined flags, which can be used to indicate some
specified status.
The WDT time-out under Normal mode or Green mode
will initialize chip reset and set the status bit TO . But
in the Sleep mode or Idle mode, the time-out will initial-
ize a warm reset and only the program counter and
stack pointer are reset to 0. To clear the WDT contents
(including the WDT prescaler), three methods are
adopted; external reset (a low level to RES pin), soft-
ware instruction and a HALT instruction.
The software instruction include CLR WDT and the
other set CLR WDT1 and CLR WDT2 . Of these two
types of instruction, only one can be active depending
on the mask option WDT instr . If the CLR WDT is se-
lected (i.e. One clear instruction), any execution of the
CLR WDT instruction will clear the WDT. In the case that
CLR WDT1 and CLR WDT2 are chosen (i.e. Two
clear instructions), these two instructions must be exe-
cuted to clear the WDT; otherwise, the WDT may reset
the chip as a result of time-out.
Controller operation mode
Holtek s telephone controllers support two system clock
and four operation modes. The system clock could be
32768Hz or 3.58MHz and operation mode could be Nor-
mal, Green, Sleep or Idle mode. These are all selected
by the software.
The following conditions will force the operation mode to
change to Green mode:
Register
Label
Bits
R/W
Function
WDTS
(09H)
WS0
WS1
WS2
0
1
2
RW
Watchdog Timer division ratio selection bits
Bit 2, 1, 0=000, Division ratio=1:1
Bit 2, 1, 0=001, Division ratio=1:2
Bit 2, 1, 0=010, Division ratio=1:4
Bit 2, 1, 0=011, Division ratio=1:8
Bit 2, 1, 0=100, Division ratio=1:16
Bit 2, 1, 0=101, Division ratio=1:32
Bit 2, 1, 0=110, Division ratio=1:64
Bit 2, 1, 0=111, Division ratio=1:128
7~3
RW
Unused bit. These bits are read/write-able.
Register
Label
Bits
R/W
Function
MODE
(26H)
4~0
RO
Unused bit, read as 0
UPEN
5
RW
1: Enable frequency up conversion function to generate 3.58MHz
0: Disable frequency up conversion function to generate 3.58MHz
MODE0
6
RW
1: Disable 32768Hz oscillator while the HALT instruction is executed
(Idle mode)
0: Enable 32768Hz oscillator while the HALT instruction is executed
(Sleep mode)
MODE1
7
RW
1: Select 3.58MHz as CPU system clock
0: Select 32768Hz as CPU system clock
Operation mode description
HALT
Instruction
MODE1
MODE0
UPEN
Operation
Mode
32768Hz
3.58MHz
System
Clock
Not execute
1
X
1
Normal
ON
ON
3.58MHz
Not execute
0
X
0
Green
ON
OFF
32768Hz
Be executed
0
0
0
Sleep
ON
OFF
HALT
Be executed
0
1
0
Idle
OFF
OFF
HALT
Note: X means don t care