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參數(shù)資料
| 型號： | HT86R384 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | Voice Synthesizer 8-Bit OTP MCU |
| 中文描述： | 語音合成器8位微控制器檢察官辦公室 |
| 文件頁數(shù)： | 20/41頁 |
| 文件大?。?/td> | 286K |
| 代理商： | HT86R384 |
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HT86R384
Rev. 0.10
20
May 18, 2007
Preliminary
Input/Output Ports
There are 23 bidirectional input/output lines in the
microcontroller, labeled from PA to PC, which are
mapped to the data memory of [12H], [14H], and [16H],
respectively. All of these I/O ports can be used for input
and output operations. For input operation, these ports
are non-latching, that is, the inputs must be ready at the
T2 rising edge of instruction MOV A, [m] (m=12H,14H
or 16H). For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC) to control the input/output configuration. With this
control register, CMOS output or Schmitt trigger input
with or without pull-high resistor structures can be re-
configured dynamically (i.e. on-the-fly) under software
control. To function as an input, the corresponding latch
of the control register must write 1 . The input source
also depends on the control register. If the control regis-
ter bit is 1 , the input will read the pad state. If the con-
trol register bit is 0 , the contents of the latches will
move to the internal bus. The latter is possible in the
read-modify-write instruction.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, and 17H. Bit 7 which is mapped to location [17H] is
always written as 1 .
Afterachipreset,theseinput/outputlinesremainathigh
levels or floating state (dependent on pull-high options).
Each bit of these input/output latches can be set or
cleared by SET [m].i and CLR [m].i (m=12H, 14H,
16H) instructions.
Some instructions first input data and then follow the
output operations. For example,
SET [m].i ,
CLR
[m].i , CPL [m] , CPLA[m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device. The wake-up capability of port A is determined
by OTP option. There is a pull-high option available for
all I/O lines. Once the pull-high option is selected, all I/O
lines have pull-high resistors. Otherwise, the pull-high
resistors are absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.
By some different OTP options, there are 3 shared pins
(PC.4, PC.5, and PC.6) in PC. They can be normal I/O
pins or for special functions. The PC.4 is the external
clock source of timer/event counter TMR0 if TMR0 is set
to external clock mode, and the PC.5 is the external
clock source of timer/event counter TMR1 if TMR1 is set
to external clock mode. PC6 is pin-shared with XIN. The
XIN and XOUT can be connected to a 32kHz crystal as
the clock source of the timer counter TMR3 if the OTP
option is set to enable 32kHz (RTC) crystal.
AudioOutputandVolumeControl
DAL,DAH,VOL
The HT86R384 provides one 12-bit voltage type DAC
device for driving external 8
nal NPN transistor. The programmer must write the
voice data to register DAL (27H) and DAH (28H). The
12-bit audio output will be written to the higher nibble of
DALand the whole byte of DAH, and the DAL3~DAL0 is
speaker through an exter-
always read as 0H . There are 8 scales of volume con-
trollable level that are provided for the voltage type DAC
output. The programmer can change the volume by only
writing the volume control data to the higher-nibble of
the VOL (29H), and the lower-nibble of VOL (29H) is al-
ways read as 0H .
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Input/Output Ports
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